[PATCH] D110231: [AMDGPU] Add constrained shift pattern matches.

[Jay Foad via Phabricator via llvm-commits]

foad added a comment.

Would it be better to do this as some kind of DAGCombine, so that other patterns involving shifts (like for v_lshl_add etc instructions) can take advantage of it too? I wonder how other targets do this. I see X86 has isUnneededShiftMask() which is used in PatFrags for shift instruction selection.



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Comment at: llvm/lib/Target/AMDGPU/SIInstructions.td:2520
+def : ConstrainedI32ShiftPat<sra, V_ASHRREV_I32_e64>;
 
 // Avoid pointlessly materializing a constant in VGPR.
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arsenm wrote:
> Should also handle scalar cases. Also consider handling 32-bit and 16-bit shifts
And 64-bit.


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  https://reviews.llvm.org/D110231/new/

https://reviews.llvm.org/D110231