[PATCH] D107658: [RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 21 23:48:18 PDT 2021
craig.topper added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:1259
+// if only the lower 32 bits of their result is used.
+class overflowingbinopw<SDPatternOperator operator>
+ : PatFrag<(ops node:$lhs, node:$rhs),
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zixuan-wu wrote:
> I am wondering could it be applied to more complicated condition with 3 operands or 1 operand? For example, mulaw, or unary operator.
We would need a different PatFrag for different number of operates, but the underlying helper function hasAllWUsers can be shared.
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https://reviews.llvm.org/D107658
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