[PATCH] D109665: [AArch64][SVE] Add patterns to generate ADR instruction

[Usman Nadeem via Phabricator via llvm-commits]

mnadeem marked an inline comment as done.
mnadeem added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:1222-1224
+  defm : adrShiftPat<nxv4i32, nxv4i1, ADR_LSL_ZZZ_S_1, 1>;
+  defm : adrShiftPat<nxv4i32, nxv4i1, ADR_LSL_ZZZ_S_2, 2>;
+  defm : adrShiftPat<nxv4i32, nxv4i1, ADR_LSL_ZZZ_S_3, 3>;
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paulwalker-arm wrote:
> These patterns are missing tests.  I suspect it's not worth the trouble trying to write a `getelementptr` based test given the i32 based addresses but doing the arithmetic explicitly in IR is good enough.
Thanks for pointing that out.
I added the tests in a new file `llvm/test/CodeGen/AArch64/sve-adr.ll` and also fixed the type for lsl's constant, which should have been i32 for S-form `adr z0.s, [z0.s, z0.s, lsl #<shift>]` 


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  https://reviews.llvm.org/D109665/new/

https://reviews.llvm.org/D109665