[PATCH] D109900: [AMDGPU] Filtering out the inactive lanes bits when lowering copy to SCC

Ruiling, Song via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Sep 21 00:14:09 PDT 2021

Previous message: [PATCH] D109900: [AMDGPU] Filtering out the inactive lanes bits when lowering copy to SCC
Next message: [PATCH] D109900: [AMDGPU] Filtering out the inactive lanes bits when lowering copy to SCC
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

ruiling added a comment.

The patch LGTM. Any different idea from others?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109900/new/

https://reviews.llvm.org/D109900

Previous message: [PATCH] D109900: [AMDGPU] Filtering out the inactive lanes bits when lowering copy to SCC
Next message: [PATCH] D109900: [AMDGPU] Filtering out the inactive lanes bits when lowering copy to SCC
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

More information about the llvm-commits mailing list