[llvm] 817e23d - [update_mir_test_checks.py] Use -NEXT FileCheck directories
Alex Richardson via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 20 04:56:25 PDT 2021
Author: Alex Richardson
Date: 2021-09-20T12:55:56+01:00
New Revision: 817e23d481be52e6e0fd779efce2beb105e8c7b6
URL: https://github.com/llvm/llvm-project/commit/817e23d481be52e6e0fd779efce2beb105e8c7b6
DIFF: https://github.com/llvm/llvm-project/commit/817e23d481be52e6e0fd779efce2beb105e8c7b6.diff
LOG: [update_mir_test_checks.py] Use -NEXT FileCheck directories
Previously the script emitted output using plain CHECK directives. This
can result in a test passing even if there are some instructions between
CHECK directives that should have been removed. It also makes debugging
tests that have the output in a different order more difficult since
FileCheck can match with a later line and then complain about the "wrong"
directive not being found.
This will cause quite large diffs when updating existing tests, but I'm not sure we need an opt-in flag here.
Depends on D109765 (pre-commit tests)
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D109767
Added:
Modified:
llvm/test/CodeGen/X86/GlobalISel/select-phi.mir
llvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/x86-condbr.mir.expected
llvm/utils/update_mir_test_checks.py
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-phi.mir b/llvm/test/CodeGen/X86/GlobalISel/select-phi.mir
index 61f58d23d98b..702da9424600 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/select-phi.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-phi.mir
@@ -118,24 +118,28 @@ registers:
body: |
; ALL-LABEL: name: test_i8
; ALL: bb.0.entry:
- ; ALL: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; ALL: liveins: $edi, $edx, $esi
- ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
- ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
- ; ALL: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
- ; ALL: [[COPY3:%[0-9]+]]:gr32 = COPY $edx
- ; ALL: [[COPY4:%[0-9]+]]:gr8 = COPY [[COPY3]].sub_8bit
- ; ALL: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
- ; ALL: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
- ; ALL: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
- ; ALL: TEST8ri [[SETCCr]], 1, implicit-def $eflags
- ; ALL: JCC_1 %bb.2, 5, implicit $eflags
- ; ALL: bb.1.cond.false:
- ; ALL: successors: %bb.2(0x80000000)
- ; ALL: bb.2.cond.end:
- ; ALL: [[PHI:%[0-9]+]]:gr8 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0
- ; ALL: $al = COPY [[PHI]]
- ; ALL: RET 0, implicit $al
+ ; ALL-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; ALL-NEXT: liveins: $edi, $edx, $esi
+ ; ALL-NEXT: {{ $}}
+ ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+ ; ALL-NEXT: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
+ ; ALL-NEXT: [[COPY3:%[0-9]+]]:gr32 = COPY $edx
+ ; ALL-NEXT: [[COPY4:%[0-9]+]]:gr8 = COPY [[COPY3]].sub_8bit
+ ; ALL-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
+ ; ALL-NEXT: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
+ ; ALL-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
+ ; ALL-NEXT: TEST8ri [[SETCCr]], 1, implicit-def $eflags
+ ; ALL-NEXT: JCC_1 %bb.2, 5, implicit $eflags
+ ; ALL-NEXT: {{ $}}
+ ; ALL-NEXT: bb.1.cond.false:
+ ; ALL-NEXT: successors: %bb.2(0x80000000)
+ ; ALL-NEXT: {{ $}}
+ ; ALL-NEXT: {{ $}}
+ ; ALL-NEXT: bb.2.cond.end:
+ ; ALL-NEXT: [[PHI:%[0-9]+]]:gr8 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0
+ ; ALL-NEXT: $al = COPY [[PHI]]
+ ; ALL-NEXT: RET 0, implicit $al
bb.1.entry:
successors: %bb.3(0x40000000), %bb.2(0x40000000)
liveins: $edi, $edx, $esi
@@ -178,24 +182,28 @@ registers:
body: |
; ALL-LABEL: name: test_i16
; ALL: bb.0.entry:
- ; ALL: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; ALL: liveins: $edi, $edx, $esi
- ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
- ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
- ; ALL: [[COPY2:%[0-9]+]]:gr16 = COPY [[COPY1]].sub_16bit
- ; ALL: [[COPY3:%[0-9]+]]:gr32 = COPY $edx
- ; ALL: [[COPY4:%[0-9]+]]:gr16 = COPY [[COPY3]].sub_16bit
- ; ALL: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
- ; ALL: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
- ; ALL: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
- ; ALL: TEST8ri [[SETCCr]], 1, implicit-def $eflags
- ; ALL: JCC_1 %bb.2, 5, implicit $eflags
- ; ALL: bb.1.cond.false:
- ; ALL: successors: %bb.2(0x80000000)
- ; ALL: bb.2.cond.end:
- ; ALL: [[PHI:%[0-9]+]]:gr16 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0
- ; ALL: $ax = COPY [[PHI]]
- ; ALL: RET 0, implicit $ax
+ ; ALL-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; ALL-NEXT: liveins: $edi, $edx, $esi
+ ; ALL-NEXT: {{ $}}
+ ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+ ; ALL-NEXT: [[COPY2:%[0-9]+]]:gr16 = COPY [[COPY1]].sub_16bit
+ ; ALL-NEXT: [[COPY3:%[0-9]+]]:gr32 = COPY $edx
+ ; ALL-NEXT: [[COPY4:%[0-9]+]]:gr16 = COPY [[COPY3]].sub_16bit
+ ; ALL-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
+ ; ALL-NEXT: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
+ ; ALL-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
+ ; ALL-NEXT: TEST8ri [[SETCCr]], 1, implicit-def $eflags
+ ; ALL-NEXT: JCC_1 %bb.2, 5, implicit $eflags
+ ; ALL-NEXT: {{ $}}
+ ; ALL-NEXT: bb.1.cond.false:
+ ; ALL-NEXT: successors: %bb.2(0x80000000)
+ ; ALL-NEXT: {{ $}}
+ ; ALL-NEXT: {{ $}}
+ ; ALL-NEXT: bb.2.cond.end:
+ ; ALL-NEXT: [[PHI:%[0-9]+]]:gr16 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0
+ ; ALL-NEXT: $ax = COPY [[PHI]]
+ ; ALL-NEXT: RET 0, implicit $ax
bb.1.entry:
successors: %bb.3(0x40000000), %bb.2(0x40000000)
liveins: $edi, $edx, $esi
@@ -237,26 +245,32 @@ registers:
body: |
; ALL-LABEL: name: test_i32
; ALL: bb.0.entry:
- ; ALL: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; ALL: liveins: $edi, $edx, $esi
- ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
- ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
- ; ALL: [[COPY2:%[0-9]+]]:gr32 = COPY $edx
- ; ALL: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
- ; ALL: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
- ; ALL: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
- ; ALL: TEST8ri [[SETCCr]], 1, implicit-def $eflags
- ; ALL: JCC_1 %bb.1, 5, implicit $eflags
- ; ALL: JMP_1 %bb.2
- ; ALL: bb.1.cond.true:
- ; ALL: successors: %bb.3(0x80000000)
- ; ALL: JMP_1 %bb.3
- ; ALL: bb.2.cond.false:
- ; ALL: successors: %bb.3(0x80000000)
- ; ALL: bb.3.cond.end:
- ; ALL: [[PHI:%[0-9]+]]:gr32 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2
- ; ALL: $eax = COPY [[PHI]]
- ; ALL: RET 0, implicit $eax
+ ; ALL-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; ALL-NEXT: liveins: $edi, $edx, $esi
+ ; ALL-NEXT: {{ $}}
+ ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+ ; ALL-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY $edx
+ ; ALL-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
+ ; ALL-NEXT: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
+ ; ALL-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
+ ; ALL-NEXT: TEST8ri [[SETCCr]], 1, implicit-def $eflags
+ ; ALL-NEXT: JCC_1 %bb.1, 5, implicit $eflags
+ ; ALL-NEXT: JMP_1 %bb.2
+ ; ALL-NEXT: {{ $}}
+ ; ALL-NEXT: bb.1.cond.true:
+ ; ALL-NEXT: successors: %bb.3(0x80000000)
+ ; ALL-NEXT: {{ $}}
+ ; ALL-NEXT: JMP_1 %bb.3
+ ; ALL-NEXT: {{ $}}
+ ; ALL-NEXT: bb.2.cond.false:
+ ; ALL-NEXT: successors: %bb.3(0x80000000)
+ ; ALL-NEXT: {{ $}}
+ ; ALL-NEXT: {{ $}}
+ ; ALL-NEXT: bb.3.cond.end:
+ ; ALL-NEXT: [[PHI:%[0-9]+]]:gr32 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2
+ ; ALL-NEXT: $eax = COPY [[PHI]]
+ ; ALL-NEXT: RET 0, implicit $eax
bb.1.entry:
successors: %bb.2(0x40000000), %bb.3(0x40000000)
liveins: $edi, $edx, $esi
@@ -302,26 +316,32 @@ registers:
body: |
; ALL-LABEL: name: test_i64
; ALL: bb.0.entry:
- ; ALL: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; ALL: liveins: $edi, $rdx, $rsi
- ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
- ; ALL: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; ALL: [[COPY2:%[0-9]+]]:gr64 = COPY $rdx
- ; ALL: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
- ; ALL: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
- ; ALL: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
- ; ALL: TEST8ri [[SETCCr]], 1, implicit-def $eflags
- ; ALL: JCC_1 %bb.1, 5, implicit $eflags
- ; ALL: JMP_1 %bb.2
- ; ALL: bb.1.cond.true:
- ; ALL: successors: %bb.3(0x80000000)
- ; ALL: JMP_1 %bb.3
- ; ALL: bb.2.cond.false:
- ; ALL: successors: %bb.3(0x80000000)
- ; ALL: bb.3.cond.end:
- ; ALL: [[PHI:%[0-9]+]]:gr64 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2
- ; ALL: $rax = COPY [[PHI]]
- ; ALL: RET 0, implicit $rax
+ ; ALL-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; ALL-NEXT: liveins: $edi, $rdx, $rsi
+ ; ALL-NEXT: {{ $}}
+ ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; ALL-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; ALL-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY $rdx
+ ; ALL-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
+ ; ALL-NEXT: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
+ ; ALL-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
+ ; ALL-NEXT: TEST8ri [[SETCCr]], 1, implicit-def $eflags
+ ; ALL-NEXT: JCC_1 %bb.1, 5, implicit $eflags
+ ; ALL-NEXT: JMP_1 %bb.2
+ ; ALL-NEXT: {{ $}}
+ ; ALL-NEXT: bb.1.cond.true:
+ ; ALL-NEXT: successors: %bb.3(0x80000000)
+ ; ALL-NEXT: {{ $}}
+ ; ALL-NEXT: JMP_1 %bb.3
+ ; ALL-NEXT: {{ $}}
+ ; ALL-NEXT: bb.2.cond.false:
+ ; ALL-NEXT: successors: %bb.3(0x80000000)
+ ; ALL-NEXT: {{ $}}
+ ; ALL-NEXT: {{ $}}
+ ; ALL-NEXT: bb.3.cond.end:
+ ; ALL-NEXT: [[PHI:%[0-9]+]]:gr64 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2
+ ; ALL-NEXT: $rax = COPY [[PHI]]
+ ; ALL-NEXT: RET 0, implicit $rax
bb.1.entry:
successors: %bb.2(0x40000000), %bb.3(0x40000000)
liveins: $edi, $rdx, $rsi
@@ -373,25 +393,29 @@ constants:
body: |
; ALL-LABEL: name: test_float
; ALL: bb.0.entry:
- ; ALL: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; ALL: liveins: $edi, $xmm0, $xmm1
- ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
- ; ALL: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
- ; ALL: [[COPY2:%[0-9]+]]:fr32 = COPY [[COPY1]]
- ; ALL: [[COPY3:%[0-9]+]]:vr128 = COPY $xmm1
- ; ALL: [[COPY4:%[0-9]+]]:fr32 = COPY [[COPY3]]
- ; ALL: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
- ; ALL: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
- ; ALL: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
- ; ALL: TEST8ri [[SETCCr]], 1, implicit-def $eflags
- ; ALL: JCC_1 %bb.2, 5, implicit $eflags
- ; ALL: bb.1.cond.false:
- ; ALL: successors: %bb.2(0x80000000)
- ; ALL: bb.2.cond.end:
- ; ALL: [[PHI:%[0-9]+]]:fr32 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0
- ; ALL: [[COPY5:%[0-9]+]]:vr128 = COPY [[PHI]]
- ; ALL: $xmm0 = COPY [[COPY5]]
- ; ALL: RET 0, implicit $xmm0
+ ; ALL-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; ALL-NEXT: liveins: $edi, $xmm0, $xmm1
+ ; ALL-NEXT: {{ $}}
+ ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; ALL-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+ ; ALL-NEXT: [[COPY2:%[0-9]+]]:fr32 = COPY [[COPY1]]
+ ; ALL-NEXT: [[COPY3:%[0-9]+]]:vr128 = COPY $xmm1
+ ; ALL-NEXT: [[COPY4:%[0-9]+]]:fr32 = COPY [[COPY3]]
+ ; ALL-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
+ ; ALL-NEXT: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
+ ; ALL-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
+ ; ALL-NEXT: TEST8ri [[SETCCr]], 1, implicit-def $eflags
+ ; ALL-NEXT: JCC_1 %bb.2, 5, implicit $eflags
+ ; ALL-NEXT: {{ $}}
+ ; ALL-NEXT: bb.1.cond.false:
+ ; ALL-NEXT: successors: %bb.2(0x80000000)
+ ; ALL-NEXT: {{ $}}
+ ; ALL-NEXT: {{ $}}
+ ; ALL-NEXT: bb.2.cond.end:
+ ; ALL-NEXT: [[PHI:%[0-9]+]]:fr32 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0
+ ; ALL-NEXT: [[COPY5:%[0-9]+]]:vr128 = COPY [[PHI]]
+ ; ALL-NEXT: $xmm0 = COPY [[COPY5]]
+ ; ALL-NEXT: RET 0, implicit $xmm0
bb.1.entry:
successors: %bb.3(0x40000000), %bb.2(0x40000000)
liveins: $edi, $xmm0, $xmm1
@@ -435,25 +459,29 @@ registers:
body: |
; ALL-LABEL: name: test_double
; ALL: bb.0.entry:
- ; ALL: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; ALL: liveins: $edi, $xmm0, $xmm1
- ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
- ; ALL: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
- ; ALL: [[COPY2:%[0-9]+]]:fr64 = COPY [[COPY1]]
- ; ALL: [[COPY3:%[0-9]+]]:vr128 = COPY $xmm1
- ; ALL: [[COPY4:%[0-9]+]]:fr64 = COPY [[COPY3]]
- ; ALL: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
- ; ALL: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
- ; ALL: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
- ; ALL: TEST8ri [[SETCCr]], 1, implicit-def $eflags
- ; ALL: JCC_1 %bb.2, 5, implicit $eflags
- ; ALL: bb.1.cond.false:
- ; ALL: successors: %bb.2(0x80000000)
- ; ALL: bb.2.cond.end:
- ; ALL: [[PHI:%[0-9]+]]:fr64 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0
- ; ALL: [[COPY5:%[0-9]+]]:vr128 = COPY [[PHI]]
- ; ALL: $xmm0 = COPY [[COPY5]]
- ; ALL: RET 0, implicit $xmm0
+ ; ALL-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; ALL-NEXT: liveins: $edi, $xmm0, $xmm1
+ ; ALL-NEXT: {{ $}}
+ ; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; ALL-NEXT: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm0
+ ; ALL-NEXT: [[COPY2:%[0-9]+]]:fr64 = COPY [[COPY1]]
+ ; ALL-NEXT: [[COPY3:%[0-9]+]]:vr128 = COPY $xmm1
+ ; ALL-NEXT: [[COPY4:%[0-9]+]]:fr64 = COPY [[COPY3]]
+ ; ALL-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
+ ; ALL-NEXT: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
+ ; ALL-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
+ ; ALL-NEXT: TEST8ri [[SETCCr]], 1, implicit-def $eflags
+ ; ALL-NEXT: JCC_1 %bb.2, 5, implicit $eflags
+ ; ALL-NEXT: {{ $}}
+ ; ALL-NEXT: bb.1.cond.false:
+ ; ALL-NEXT: successors: %bb.2(0x80000000)
+ ; ALL-NEXT: {{ $}}
+ ; ALL-NEXT: {{ $}}
+ ; ALL-NEXT: bb.2.cond.end:
+ ; ALL-NEXT: [[PHI:%[0-9]+]]:fr64 = PHI [[COPY4]], %bb.1, [[COPY2]], %bb.0
+ ; ALL-NEXT: [[COPY5:%[0-9]+]]:vr128 = COPY [[PHI]]
+ ; ALL-NEXT: $xmm0 = COPY [[COPY5]]
+ ; ALL-NEXT: RET 0, implicit $xmm0
bb.1.entry:
successors: %bb.3(0x40000000), %bb.2(0x40000000)
liveins: $edi, $xmm0, $xmm1
diff --git a/llvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/x86-condbr.mir.expected b/llvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/x86-condbr.mir.expected
index 61798e2fbbeb..12460d3332c5 100644
--- a/llvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/x86-condbr.mir.expected
+++ b/llvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/x86-condbr.mir.expected
@@ -29,20 +29,23 @@ registers:
body: |
; CHECK-LABEL: name: test
; CHECK: bb.0.entry:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
- ; CHECK: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
- ; CHECK: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 1
- ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
- ; CHECK: TEST8ri [[COPY1]], 1, implicit-def $eflags
- ; CHECK: JCC_1 %bb.1, 5, implicit $eflags
- ; CHECK: JMP_1 %bb.2
- ; CHECK: bb.1.true:
- ; CHECK: $eax = COPY [[MOV32r0_]]
- ; CHECK: RET 0, implicit $eax
- ; CHECK: bb.2.false:
- ; CHECK: $eax = COPY [[MOV32ri]]
- ; CHECK: RET 0, implicit $eax
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
+ ; CHECK-NEXT: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
+ ; CHECK-NEXT: TEST8ri [[COPY1]], 1, implicit-def $eflags
+ ; CHECK-NEXT: JCC_1 %bb.1, 5, implicit $eflags
+ ; CHECK-NEXT: JMP_1 %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.true:
+ ; CHECK-NEXT: $eax = COPY [[MOV32r0_]]
+ ; CHECK-NEXT: RET 0, implicit $eax
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.false:
+ ; CHECK-NEXT: $eax = COPY [[MOV32ri]]
+ ; CHECK-NEXT: RET 0, implicit $eax
bb.1.entry:
successors: %bb.2(0x40000000), %bb.3(0x40000000)
liveins: $edi
diff --git a/llvm/utils/update_mir_test_checks.py b/llvm/utils/update_mir_test_checks.py
index c1590c55637e..d50ab41366d3 100755
--- a/llvm/utils/update_mir_test_checks.py
+++ b/llvm/utils/update_mir_test_checks.py
@@ -220,10 +220,13 @@ def add_check_lines(test, output_lines, prefix, func_name, single_bb,
check = '{:>{}}; {}'.format('', indent, prefix)
output_lines.append('{}-LABEL: name: {}'.format(check, func_name))
+ first_check = True
vreg_map = {}
for func_line in func_body:
if not func_line.strip():
+ # The mir printer prints leading whitespace so we can't use CHECK-EMPTY:
+ output_lines.append(check + '-NEXT: {{' + func_line + '$}}')
continue
m = VREG_DEF_RE.match(func_line)
if m:
@@ -235,7 +238,9 @@ def add_check_lines(test, output_lines, prefix, func_name, single_bb,
for number, name in vreg_map.items():
func_line = re.sub(r'{}\b'.format(number), '[[{}]]'.format(name),
func_line)
- check_line = '{}: {}'.format(check, func_line[indent:]).rstrip()
+ filecheck_directive = check if first_check else check + '-NEXT'
+ first_check = False
+ check_line = '{}: {}'.format(filecheck_directive, func_line[indent:]).rstrip()
output_lines.append(check_line)
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