[PATCH] D109900: [AMDGPU] Filtering out the inactive lanes bits when lowering copy to SCC

[Ruiling, Song via Phabricator via llvm-commits]

ruiling added a comment.

IMO, it is more useful to use an end-to-end test ( from LLVM IR to assembly). We do lots of work scattered in different places to deal with boolean values. Things may change in the future, and we may move this logic to other passes.
Btw, I don't know why you were creating a file with the mode 755. I don't know whether it matters in a patch.



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Comment at: llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp:604
                     .addImm(0);
-            BuildMI(*MI.getParent(), std::next(I), I->getDebugLoc(),
-                    TII->get(AMDGPU::COPY), DstReg)
-                .addReg(SCCCopy);
+            I = BuildMI(*MI.getParent(), std::next(I), I->getDebugLoc(),
+                        TII->get(AMDGPU::COPY), DstReg)
----------------
I guess this is just used to skip the newly inserted instruction, no functional change?


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Comment at: llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp:612
+                ST.isWave64() ? AMDGPU::S_AND_B64 : AMDGPU::S_AND_B32;
+            Register EXEC = ST.isWave64() ? AMDGPU::EXEC : AMDGPU::EXEC_LO;
+            Register Tmp = MRI->createVirtualRegister(TRI->getBoolRC());
----------------
Please use `Exec` as variable name.


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