[PATCH] D109900: [AMDGPU] Filtering out the inactive lanes bits when lowering copy to SCC

[Alexander via Phabricator via llvm-commits]

alex-t updated this revision to Diff 373303.
alex-t added a comment.

- detailed summary
- MIR test added
- formatting corrected


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109900/new/

https://reviews.llvm.org/D109900

Files:
  llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
  llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
  llvm/test/CodeGen/AMDGPU/copy_to_scc.mir

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