[PATCH] D109162: [RISCV] Select (srl (sext_inreg X, i32), uimm5) to SRAIW if only lower 32 bits are used.

[Craig Topper via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG73e5b9ea90ba: [RISCV] Select (srl (sext_inreg X, i32), uimm5) to SRAIW if only lower 32 bits… (authored by craig.topper).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109162/new/

https://reviews.llvm.org/D109162

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoM.td
  llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
  llvm/test/CodeGen/RISCV/srem-lkk.ll

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