[PATCH] D109162: [RISCV] Select (srl (sext_inreg X, i32), uimm5) to SRAIW if only lower 32 bits are used.

Luís Marques via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Sep 16 03:25:57 PDT 2021

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luismarques accepted this revision.
luismarques added a comment.
This revision is now accepted and ready to land.

LGTM.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109162/new/

https://reviews.llvm.org/D109162

Previous message: [PATCH] D109577: [LNT] Fixed incorrect orders behavior in case of miss formatted llvm_project_revision
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