[PATCH] D109808: [InstCombine] Eliminate vector reverse if all inputs/outputs to an instruction are reverses

[Caroline via Phabricator via llvm-commits]

CarolineConcatto added a comment.

@mnadeem Nice patch.
I believe you need to test the other way around for binary operations, no?
I left a comment, I hope it makes sense.



================
Comment at: llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp:2053
+    // rev(binop rev(X), rev(Y)) --> binop X, Y
+    // rev(binop rev(X), Splat) --> binop X, Splat
+    if (match(
----------------
Why are you not simplifying
 rev(binop  Splat, rev(X)) --> binop, Splat,  X.
too?
When I run this test:

```
define <vscale x 4 x i32> @binop_reverse_splat(<vscale x 4 x i32> %a, i32 %b) {
  %reva = tail call <vscale x 4 x i32> @llvm.experimental.vector.reverse.nxv4i32(<vscale x 4 x i32> %a)
  %splat_insert = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
  %splat = shufflevector <vscale x 4 x i32> %splat_insert, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
  %add = add <vscale x 4 x i32> %splat, %reva
  %revadd = tail call <vscale x 4 x i32> @llvm.experimental.vector.reverse.nxv4i32(<vscale x 4 x i32> %add)
  ret <vscale x 4 x i32> %revadd
}
```
I do not see any simplification.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D109808/new/

https://reviews.llvm.org/D109808