[PATCH] D109808: [InstCombine] Eliminate vector reverse if all inputs/outputs to an instruction are reverses

[Usman Nadeem via Phabricator via llvm-commits]

mnadeem created this revision.
mnadeem added reviewers: CarolineConcatto, david-arm, sdesmalen.
Herald added a subscriber: hiraditya.
mnadeem requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D109808

Files:
  llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
  llvm/test/Transforms/InstCombine/vector-reverse.ll
  llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse-mask4.ll
  llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse.ll

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