[PATCH] D109754: AMDGPU: Use -1/0 when copying from SCC to SGPR
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 14 05:46:24 PDT 2021
arsenm added a comment.
In D109754#2999491 <https://reviews.llvm.org/D109754#2999491>, @arsenm wrote:
> In D109754#2999478 <https://reviews.llvm.org/D109754#2999478>, @piotr wrote:
>
>> The change makes sense to me in general.
>>
>> When I tried doing the same long time ago, Matt rightly pointed out (https://reviews.llvm.org/D81925#inline-753225) that sign extending does not correspond to the booleans being defined as zero extended. So, wouldn't your change also require an accompanying change of boolean contents to ZeroOrNegativeOneBooleanContent instead of ZeroOrOneBooleanContent in SIISelLowering.cpp?
>
> No, because this is producing a mask and not really an extended value
Well in this context it's ambiguous since we don't know what the destination register is used for. I think this is a problem earlier in the flow
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D109754/new/
https://reviews.llvm.org/D109754
More information about the llvm-commits
mailing list