[PATCH] D109587: [RISCV][WIP] Generate target attribute in attribute section of object file when assemble .s file

[Zixuan Wu via Phabricator via llvm-commits]

zixuan-wu created this revision.
zixuan-wu added a reviewer: MaskRay.
Herald added subscribers: vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
zixuan-wu requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

When there is not RISCV arch attribute in assembly .s file, it will not generate arch attribute in obj file. LLVM asm parser does not use subtarget feature bits to generate appropriate attributes. So instructions can not be recognized in disassemble process (llvm-objdump).

It's a WIP patch to discuss and see whether the direction is right.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D109587

Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/test/CodeGen/RISCV/branch-relaxation.ll
  llvm/test/CodeGen/RISCV/inline-asm-S-constraint.ll
  llvm/test/CodeGen/RISCV/inline-asm-d-abi-names.ll
  llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
  llvm/test/CodeGen/RISCV/inline-asm-f-abi-names.ll
  llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
  llvm/test/CodeGen/RISCV/large-stack.ll
  llvm/test/CodeGen/RISCV/rvv/inline-asm.ll
  llvm/test/MC/RISCV/fde-reloc.s
  llvm/test/MC/RISCV/rvf-user-csr-names.s

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D109587.371836.patch
Type: text/x-patch
Size: 96710 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210910/99441a04/attachment-0001.bin>