[PATCH] D109323: [AArch64] Improve adrp schedule modelling on the Cortex-A55

[Nicholas Guy via Phabricator via llvm-commits]

NickGuy updated this revision to Diff 371823.
NickGuy added a comment.

Updated test


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109323/new/

https://reviews.llvm.org/D109323

Files:
  llvm/lib/Target/AArch64/AArch64.td
  llvm/test/CodeGen/AArch64/a55-fuse-address.mir


Index: llvm/test/CodeGen/AArch64/a55-fuse-address.mir
===================================================================
--- llvm/test/CodeGen/AArch64/a55-fuse-address.mir
+++ llvm/test/CodeGen/AArch64/a55-fuse-address.mir
@@ -30,8 +30,8 @@
     ; CHECK-LABEL: name: fuseaddress
     ; CHECK: liveins: $w0
     ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @a
-    ; CHECK: [[ADRP1:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @b
     ; CHECK: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @a :: (dereferenceable load (s32) from @a)
+    ; CHECK: [[ADRP1:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @b
     ; CHECK: [[LDRWui1:%[0-9]+]]:gpr32 = LDRWui [[ADRP1]], target-flags(aarch64-pageoff, aarch64-nc) @b :: (dereferenceable load (s32) from @b)
     ; CHECK: [[MADDWrrr:%[0-9]+]]:gpr32 = nsw MADDWrrr [[LDRWui]], [[LDRWui1]], $wzr
     ; CHECK: $w0 = COPY [[MADDWrrr]]
Index: llvm/lib/Target/AArch64/AArch64.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64.td
+++ llvm/lib/Target/AArch64/AArch64.td
@@ -616,6 +616,7 @@
                                    FeatureRCPC,
                                    FeaturePerfMon,
                                    FeaturePostRAScheduler,
+                                   FeatureFuseAddress,
                                    ]>;
 
 def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",


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