[PATCH] D108602: [RISCV] Initial support .insn directive for the assembler.

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


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Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:2261
+                                 ErrorInfo,
+                                 /* MatchingInlineAsm */ false);
+}
----------------



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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:881
+def InsnR : DirectiveInsnR<(outs), (ins uimm7:$opcode, uimm3:$funct3,
+                                        uimm7:$funct7, AnyReg:$rd,
+                                        AnyReg:$rs1, AnyReg:$rs2),
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We should probably be marking rd as outs? In a way it doesn't matter (though downstream I think I'll need to inspect the register used for `rd` to know which relocation to use for jumps; currently I just look at the opcode in RISCVMCCodeEmitter::getImmOpValue but that'll become the ambiguous InsnJ and, eventually, InsnCJ and being able to just get the first def to see what register it is would be slightly easier than having to hard-code which operand number it is) but is technically wrong currently.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108602/new/

https://reviews.llvm.org/D108602