[PATCH] D109394: [RISCV] Enable CGP to sink splat operands of Add/Sub/Mul.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1062
+      continue;
+    if (!IsSinker(I, OpIdx.index()))
+      continue;
----------------
Is it worth performing this check before the `match`? I'm assuming this early-exits more often and more cheaply than the `match`.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1049
+
+      ShuffleVectorInst *Shuffle = dyn_cast<ShuffleVectorInst>(Op);
+      if (!Shuffle || !Shuffle->isZeroEltSplat())
----------------
craig.topper wrote:
> frasercrmck wrote:
> > Do you think the IR pattern matching library would be appropriate to use here?
> > 
> > While I'm on that subject, do you think it's worth separating this logic out into a new pattern matcher (e.g. `m_VectorSplat`) if there isn't one already?
> I've switched to basing this on ARM's implementation which uses PatternMatch. I dropped the code for looking through a bitcast though. I'm uncomfortable using an m_VectorSplat because of the `Ops.push_back(&Op->getOperandUse(0))`. We need to know exactly what instructions we matched for that to be correct.
Yeah I think this is an improvement, thanks. Fair enough on `m_VectorSplat`; I hadn't fully understood exactly what we're supposed to return in this vector.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109394/new/

https://reviews.llvm.org/D109394