[PATCH] D109394: [RISCV] Enable CGP to sink splat operands of Add/Sub/Mul.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 8 10:58:32 PDT 2021
craig.topper added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1049
+
+ ShuffleVectorInst *Shuffle = dyn_cast<ShuffleVectorInst>(Op);
+ if (!Shuffle || !Shuffle->isZeroEltSplat())
----------------
frasercrmck wrote:
> Do you think the IR pattern matching library would be appropriate to use here?
>
> While I'm on that subject, do you think it's worth separating this logic out into a new pattern matcher (e.g. `m_VectorSplat`) if there isn't one already?
I've switched to basing this on ARM's implementation which uses PatternMatch. I dropped the code for looking through a bitcast though. I'm uncomfortable using an m_VectorSplat because of the `Ops.push_back(&Op->getOperandUse(0))`. We need to know exactly what instructions we matched for that to be correct.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D109394/new/
https://reviews.llvm.org/D109394
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