[PATCH] D109423: [PowerPC] Reduce number of virtual registers used when eliminating frameindex

[Kai Luo via Phabricator via llvm-commits]

lkail created this revision.
lkail added reviewers: PowerPC, nemanjai, jsji, shchenz.
Herald added subscribers: arphaman, kbarton, hiraditya.
lkail requested review of this revision.
Herald added a project: LLVM.
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When eliminating frameindex, we don't need two virtual registers to materialize a int32 immediate. No test is changed since `SRegHi` is set killed and Scavenger allocates the same physical register for `SReg` and `SRegHi`.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D109423

Files:
  llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp


Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -1476,18 +1476,17 @@
   const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
   const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
   const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC;
-  Register SRegHi = MF.getRegInfo().createVirtualRegister(RC),
-           SReg = MF.getRegInfo().createVirtualRegister(RC);
+  Register SReg = MF.getRegInfo().createVirtualRegister(RC);
 
   // Insert a set of rA with the full offset value before the ld, st, or add
   if (isInt<16>(Offset))
     BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI), SReg)
       .addImm(Offset);
   else {
-    BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi)
+    BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SReg)
       .addImm(Offset >> 16);
     BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
-      .addReg(SRegHi, RegState::Kill)
+      .addReg(SReg, RegState::Kill)
       .addImm(Offset);
   }
 


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