[PATCH] D109146: [AArch64][SVE] Replace fmul and fadd LLVM IR instrinsics with fmul and fadd

[Bradley Smith via Phabricator via llvm-commits]

bsmith added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp:702-707
+    auto *PTrueIntrinsic = dyn_cast<IntrinsicInst>(OperandValue);
+    const uint64_t PTruePattern =
+        cast<ConstantInt>(PTrueIntrinsic->getOperand(0))->getZExtValue();
+    if (PTruePattern != AArch64SVEPredPattern::all) {
+      return None;
+    }
----------------
This is not taking into consideration the type of the ptrue, this could be an i64 type ptrue passed to an i32 type mul/add, hence does not cover all lanes of the operation. There needs to be a check in here that checks that the ptrue type is the same or smaller than the predicated operation. For example, for a `<vscale x 4 x i32>` vector op, only ptrue types of  `<vscale x 4 x i1>`, `<vscale x 8 x i1>`, `<vscale x 16 x i1>` are allowed, `<vscale x 2 x i1>` is not.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109146/new/

https://reviews.llvm.org/D109146