[PATCH] D109295: [X86] Handle inverted inputs when matching VPTERNLOG from 2 binary ops.

[LuoYuanke via Phabricator via llvm-commits]

LuoYuanke added inline comments.


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Comment at: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:4232
+  if (IsNot(A)) {
+    TernlogMagicA = ~TernlogMagicA;
+    ParentA = A.getNode();
----------------
It seems for VPTERNLOG instruction we can accept the 4th operand whose value is allZero or allOne no matter what is logic operation is.


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Comment at: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:4234
+    ParentA = A.getNode();
+    A = A.getOperand(0);
+  }
----------------
Is the constant operand canonicalized as operand(1)?


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Comment at: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:4246
+    ParentC = C.getNode();
+    C = B.getOperand(0);
+  }
----------------
C.getOperand(0)?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109295/new/

https://reviews.llvm.org/D109295