[llvm] 0d0f39b - [X86][Atom] Add missing UOps override to AtomWriteResPair multiclass

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2021-09-04T11:58:09+01:00
New Revision: 0d0f39b0f3ee3b7d41a6caca6896a90d1a316437

URL: https://github.com/llvm/llvm-project/commit/0d0f39b0f3ee3b7d41a6caca6896a90d1a316437
DIFF: https://github.com/llvm/llvm-project/commit/0d0f39b0f3ee3b7d41a6caca6896a90d1a316437.diff

LOG: [X86][Atom] Add missing UOps override to AtomWriteResPair multiclass

Make it easier to describe microcoded instructions.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ScheduleAtom.td

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86ScheduleAtom.td b/llvm/lib/Target/X86/X86ScheduleAtom.td
index eaed2aa05c1ed..7a02f5834b265 100644
--- a/llvm/lib/Target/X86/X86ScheduleAtom.td
+++ b/llvm/lib/Target/X86/X86ScheduleAtom.td
@@ -56,17 +56,21 @@ multiclass AtomWriteResPair<X86FoldableSchedWrite SchedRW,
                             list<ProcResourceKind> RMPorts,
                             int RRLat = 1, int RMLat = 1,
                             list<int> RRRes = [1],
-                            list<int> RMRes = [1]> {
+                            list<int> RMRes = [1],
+                            int RRUOps = 1,
+                            int RMUOps = 1> {
   // Register variant.
   def : WriteRes<SchedRW, RRPorts> {
     let Latency = RRLat;
     let ResourceCycles = RRRes;
+    let NumMicroOps = RRUOps;
   }
 
   // Memory variant.
   def : WriteRes<SchedRW.Folded, RMPorts> {
     let Latency = RMLat;
     let ResourceCycles = RMRes;
+    let NumMicroOps = RMUOps;
   }
 }