[PATCH] D109260: [RISCV] Add SiFive cores E and S series

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/include/llvm/Support/RISCVTargetParser.def:24
+PROC(SIFIVE_E21, {"sifive-e21"}, FK_NONE, {"rv32imac"})
+PROC(SIFIVE_E34, {"sifive-e24"}, FK_NONE, {"rv32imafc"})
 PROC(SIFIVE_E31, {"sifive-e31"}, FK_NONE, {"rv32imac"})
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Should SIFIVE_E34 be SIFIVE_E24?


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Comment at: llvm/include/llvm/Support/RISCVTargetParser.def:31
+PROC(SIFIVE_S54, {"sifive-s54"}, FK_64BIT, {"rv64gc"})
+PROC(SIFIVE_U74, {"sifive-s76"}, FK_64BIT, {"rv64gc"})
 PROC(SIFIVE_U54, {"sifive-u54"}, FK_64BIT, {"rv64gc"})
----------------
Should SIFIVE_U74 be SIFIVE_S76?


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Comment at: llvm/lib/Target/RISCV/RISCV.td:279
+
+def : ProcessorModel<"sifive-s21", RocketModel, [Feature64Bit,
+                                                 FeatureStdExtM,
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Can we sort these by leading digit, then by letter? That will keep most of the SiFive7Models together.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109260/new/

https://reviews.llvm.org/D109260