[PATCH] D109260: [RISCV] Add SiFive cores E and S series

[Alexander Pivovarov via Phabricator via llvm-commits]

apivovarov updated this revision to Diff 370683.
apivovarov retitled this revision from "[RISCV] Add SiFive core E20" to "[RISCV] Add SiFive cores E and S series".
apivovarov edited the summary of this revision.
apivovarov added a comment.

Added SiFive cores E20, E21, E24, E34, S21, S54 and S76


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109260/new/

https://reviews.llvm.org/D109260

Files:
  clang/docs/ReleaseNotes.rst
  clang/test/Driver/riscv-cpus.c
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/include/llvm/Support/RISCVTargetParser.def
  llvm/lib/Target/RISCV/RISCV.td

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