[PATCH] D109260: [RISCV] Add SiFive core E20

Alexander Pivovarov via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Sep 3 15:09:33 PDT 2021


apivovarov added a comment.

Another missing combination is:

- e24 and e34 (rocket, rv32imafc)

I can also add several cores which are similar to existing cores:

- e21 (same as existing e31 - rocket, rv32imac)
- s21 (same as existing s51 - rocket, rv64imac)
- s54 (same as existing u54 - rocket, rv64imafdc)
- s76  (same as existing u74 - SiFive7, rv64imafdc)

To match gcc cores definition - https://github.com/gcc-mirror/gcc/blob/master/gcc/config/riscv/riscv-cores.def#L34


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D109260/new/

https://reviews.llvm.org/D109260



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