[llvm] 1104e32 - Fix typo in RISCVMatInt.cpp comments

[Alexander Pivovarov via llvm-commits]

Author: Alexander Pivovarov
Date: 2021-09-02T18:11:09-07:00
New Revision: 1104e3258b5064e7110cc297e2cec60ac9acfc0a

URL: https://github.com/llvm/llvm-project/commit/1104e3258b5064e7110cc297e2cec60ac9acfc0a
DIFF: https://github.com/llvm/llvm-project/commit/1104e3258b5064e7110cc297e2cec60ac9acfc0a.diff

LOG: Fix typo in RISCVMatInt.cpp comments

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
index 2ca5eeb8392ef..af0434e9a7834 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
@@ -77,7 +77,7 @@ static void generateInstSeqImpl(int64_t Val,
   assert(IsRV64 && "Can't emit >32-bit imm for non-RV64 target");
 
   // In the worst case, for a full 64-bit constant, a sequence of 8 instructions
-  // (i.e., LUI+ADDIW+SLLI+ADDI+SLLI+ADDI+SLLI+ADDI) has to be emmitted. Note
+  // (i.e., LUI+ADDIW+SLLI+ADDI+SLLI+ADDI+SLLI+ADDI) has to be emitted. Note
   // that the first two instructions (LUI+ADDIW) can contribute up to 32 bits
   // while the following ADDI instructions contribute up to 12 bits each.
   //