[llvm] 78fbd1a - [AMDGPU] Process any power of 2 in optimizeCompareInstr
Stanislav Mekhanoshin via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 2 17:39:27 PDT 2021
Author: Stanislav Mekhanoshin
Date: 2021-09-02T17:39:17-07:00
New Revision: 78fbd1aa3da4da318f6ee8d269f1f4002d19a7ff
URL: https://github.com/llvm/llvm-project/commit/78fbd1aa3da4da318f6ee8d269f1f4002d19a7ff
DIFF: https://github.com/llvm/llvm-project/commit/78fbd1aa3da4da318f6ee8d269f1f4002d19a7ff.diff
LOG: [AMDGPU] Process any power of 2 in optimizeCompareInstr
Differential Revision: https://reviews.llvm.org/D109201
Added:
llvm/test/CodeGen/AMDGPU/optimize-compare.ll
Modified:
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/test/CodeGen/AMDGPU/optimize-compare.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 5b3777a0bd7f..5d9e0e34fafd 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -8020,38 +8020,30 @@ bool SIInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
return false;
const auto optimizeCmpAnd = [&CmpInstr, SrcReg, CmpValue, MRI,
- this](int64_t ExpectedValue,
- unsigned SrcSize,
- bool IsReversable) -> bool {
- // s_cmp_eq_u32 (s_and_b32 $src, 1), 1 => s_and_b32 $src, 1
- // s_cmp_eq_i32 (s_and_b32 $src, 1), 1 => s_and_b32 $src, 1
- // s_cmp_ge_u32 (s_and_b32 $src, 1), 1 => s_and_b32 $src, 1
- // s_cmp_ge_i32 (s_and_b32 $src, 1), 1 => s_and_b32 $src, 1
- // s_cmp_eq_u64 (s_and_b64 $src, 1), 1 => s_and_b64 $src, 1
- // s_cmp_lg_u32 (s_and_b32 $src, 1), 0 => s_and_b32 $src, 1
- // s_cmp_lg_i32 (s_and_b32 $src, 1), 0 => s_and_b32 $src, 1
- // s_cmp_gt_u32 (s_and_b32 $src, 1), 0 => s_and_b32 $src, 1
- // s_cmp_gt_i32 (s_and_b32 $src, 1), 0 => s_and_b32 $src, 1
- // s_cmp_lg_u64 (s_and_b64 $src, 1), 0 => s_and_b64 $src, 1
+ this](int64_t ExpectedValue, unsigned SrcSize,
+ bool IsReversable, bool IsSigned) -> bool {
+ // s_cmp_eq_u32 (s_and_b32 $src, 1 << n), 1 << n => s_and_b32 $src, 1 << n
+ // s_cmp_eq_i32 (s_and_b32 $src, 1 << n), 1 << n => s_and_b32 $src, 1 << n
+ // s_cmp_ge_u32 (s_and_b32 $src, 1 << n), 1 << n => s_and_b32 $src, 1 << n
+ // s_cmp_ge_i32 (s_and_b32 $src, 1 << n), 1 << n => s_and_b32 $src, 1 << n
+ // s_cmp_eq_u64 (s_and_b64 $src, 1 << n), 1 << n => s_and_b64 $src, 1 << n
+ // s_cmp_lg_u32 (s_and_b32 $src, 1 << n), 0 => s_and_b32 $src, 1 << n
+ // s_cmp_lg_i32 (s_and_b32 $src, 1 << n), 0 => s_and_b32 $src, 1 << n
+ // s_cmp_gt_u32 (s_and_b32 $src, 1 << n), 0 => s_and_b32 $src, 1 << n
+ // s_cmp_gt_i32 (s_and_b32 $src, 1 << n), 0 => s_and_b32 $src, 1 << n
+ // s_cmp_lg_u64 (s_and_b64 $src, 1 << n), 0 => s_and_b64 $src, 1 << n
+ //
+ // Signed ge/gt are not used for the sign bit.
//
// If result of the AND is unused except in the compare:
- // s_and_b(32|64) $src, 1 => s_bitcmp1_b(32|64) $src, 0
+ // s_and_b(32|64) $src, 1 << n => s_bitcmp1_b(32|64) $src, n
//
- // s_cmp_eq_u32 (s_and_b32 $src, 1), 0 => s_bitcmp0_b32 $src, 0
- // s_cmp_eq_i32 (s_and_b32 $src, 1), 0 => s_bitcmp0_b32 $src, 0
- // s_cmp_eq_u64 (s_and_b64 $src, 1), 0 => s_bitcmp0_b64 $src, 0
- // s_cmp_lg_u32 (s_and_b32 $src, 1), 1 => s_bitcmp0_b32 $src, 0
- // s_cmp_lg_i32 (s_and_b32 $src, 1), 1 => s_bitcmp0_b32 $src, 0
- // s_cmp_lg_u64 (s_and_b64 $src, 1), 1 => s_bitcmp0_b64 $src, 0
-
- bool IsReversedCC = false;
- if (CmpValue != ExpectedValue) {
- if (!IsReversable)
- return false;
- IsReversedCC = CmpValue == (ExpectedValue ^ 1);
- if (!IsReversedCC)
- return false;
- }
+ // s_cmp_eq_u32 (s_and_b32 $src, 1 << n), 0 => s_bitcmp0_b32 $src, n
+ // s_cmp_eq_i32 (s_and_b32 $src, 1 << n), 0 => s_bitcmp0_b32 $src, n
+ // s_cmp_eq_u64 (s_and_b64 $src, 1 << n), 0 => s_bitcmp0_b64 $src, n
+ // s_cmp_lg_u32 (s_and_b32 $src, 1 << n), 1 << n => s_bitcmp0_b32 $src, n
+ // s_cmp_lg_i32 (s_and_b32 $src, 1 << n), 1 << n => s_bitcmp0_b32 $src, n
+ // s_cmp_lg_u64 (s_and_b64 $src, 1 << n), 1 << n => s_bitcmp0_b64 $src, n
MachineInstr *Def = MRI->getUniqueVRegDef(SrcReg);
if (!Def || Def->getParent() != CmpInstr.getParent())
@@ -8061,13 +8053,14 @@ bool SIInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
Def->getOpcode() != AMDGPU::S_AND_B64)
return false;
- const auto isMask = [](const MachineOperand *MO) -> bool {
- int64_t Mask;
+ int64_t Mask;
+ const auto isMask = [&Mask, SrcSize](const MachineOperand *MO) -> bool {
if (MO->isImm())
Mask = MO->getImm();
else if (!getFoldableImm(MO, Mask))
return false;
- return Mask == 1;
+ Mask &= maxUIntN(SrcSize);
+ return isPowerOf2_64(Mask);
};
MachineOperand *SrcOp = &Def->getOperand(1);
@@ -8078,6 +8071,21 @@ bool SIInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
else
return false;
+ unsigned BitNo = countTrailingZeros((uint64_t)Mask);
+ if (IsSigned && BitNo == SrcSize - 1)
+ return false;
+
+ ExpectedValue <<= BitNo;
+
+ bool IsReversedCC = false;
+ if (CmpValue != ExpectedValue) {
+ if (!IsReversable)
+ return false;
+ IsReversedCC = CmpValue == (ExpectedValue ^ Mask);
+ if (!IsReversedCC)
+ return false;
+ }
+
Register DefReg = Def->getOperand(0).getReg();
if (IsReversedCC && !MRI->hasOneNonDBGUse(DefReg))
return false;
@@ -8099,8 +8107,6 @@ bool SIInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
}
// Replace AND with unused result with a S_BITCMP.
- // TODO: If s_bitcmp can be used we are not limited to 1 and 0 but can
- // process any power of 2.
MachineBasicBlock *MBB = Def->getParent();
unsigned NewOpc = (SrcSize == 32) ? IsReversedCC ? AMDGPU::S_BITCMP0_B32
@@ -8110,7 +8116,7 @@ bool SIInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
BuildMI(*MBB, Def, Def->getDebugLoc(), get(NewOpc))
.add(*SrcOp)
- .addImm(0);
+ .addImm(Log2_64(Mask));
Def->eraseFromParent();
return true;
@@ -8123,26 +8129,28 @@ bool SIInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
case AMDGPU::S_CMP_EQ_I32:
case AMDGPU::S_CMPK_EQ_U32:
case AMDGPU::S_CMPK_EQ_I32:
- return optimizeCmpAnd(1, 32, true);
+ return optimizeCmpAnd(1, 32, true, false);
case AMDGPU::S_CMP_GE_U32:
- case AMDGPU::S_CMP_GE_I32:
case AMDGPU::S_CMPK_GE_U32:
+ return optimizeCmpAnd(1, 32, false, false);
+ case AMDGPU::S_CMP_GE_I32:
case AMDGPU::S_CMPK_GE_I32:
- return optimizeCmpAnd(1, 32, false);
+ return optimizeCmpAnd(1, 32, false, true);
case AMDGPU::S_CMP_EQ_U64:
- return optimizeCmpAnd(1, 64, true);
+ return optimizeCmpAnd(1, 64, true, false);
case AMDGPU::S_CMP_LG_U32:
case AMDGPU::S_CMP_LG_I32:
case AMDGPU::S_CMPK_LG_U32:
case AMDGPU::S_CMPK_LG_I32:
- return optimizeCmpAnd(0, 32, true);
+ return optimizeCmpAnd(0, 32, true, false);
case AMDGPU::S_CMP_GT_U32:
- case AMDGPU::S_CMP_GT_I32:
case AMDGPU::S_CMPK_GT_U32:
+ return optimizeCmpAnd(0, 32, false, false);
+ case AMDGPU::S_CMP_GT_I32:
case AMDGPU::S_CMPK_GT_I32:
- return optimizeCmpAnd(0, 32, false);
+ return optimizeCmpAnd(0, 32, false, true);
case AMDGPU::S_CMP_LG_U64:
- return optimizeCmpAnd(0, 64, true);
+ return optimizeCmpAnd(0, 64, true, false);
}
return false;
diff --git a/llvm/test/CodeGen/AMDGPU/optimize-compare.ll b/llvm/test/CodeGen/AMDGPU/optimize-compare.ll
new file mode 100644
index 000000000000..28be3738c658
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/optimize-compare.ll
@@ -0,0 +1,80 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+
+define amdgpu_kernel void @if_masked_1(i32 %arg, i32 addrspace(1)* %p) {
+; GCN-LABEL: if_masked_1:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dword s4, s[0:1], 0x24
+; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
+; GCN-NEXT: v_mov_b32_e32 v0, 0
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_bitcmp0_b32 s4, 0
+; GCN-NEXT: s_cselect_b32 s0, 22, 33
+; GCN-NEXT: v_mov_b32_e32 v1, s0
+; GCN-NEXT: global_store_dword v0, v1, s[2:3]
+; GCN-NEXT: s_endpgm
+ %and = and i32 %arg, 1
+ %cmp = icmp eq i32 %and, 0
+ %sel = select i1 %cmp, i32 22, i32 33
+ store i32 %sel, i32 addrspace(1)* %p
+ ret void
+}
+
+define amdgpu_kernel void @if_masked_1024(i32 %arg, i32 addrspace(1)* %p) {
+; GCN-LABEL: if_masked_1024:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dword s4, s[0:1], 0x24
+; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
+; GCN-NEXT: v_mov_b32_e32 v0, 0
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_bitcmp0_b32 s4, 10
+; GCN-NEXT: s_cselect_b32 s0, 22, 33
+; GCN-NEXT: v_mov_b32_e32 v1, s0
+; GCN-NEXT: global_store_dword v0, v1, s[2:3]
+; GCN-NEXT: s_endpgm
+ %and = and i32 %arg, 1024
+ %cmp = icmp eq i32 %and, 0
+ %sel = select i1 %cmp, i32 22, i32 33
+ store i32 %sel, i32 addrspace(1)* %p
+ ret void
+}
+
+define amdgpu_kernel void @if_masked_0x80000000(i32 %arg, i32 addrspace(1)* %p) {
+; GCN-LABEL: if_masked_0x80000000:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dword s4, s[0:1], 0x24
+; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
+; GCN-NEXT: v_mov_b32_e32 v0, 0
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_bitcmp0_b32 s4, 31
+; GCN-NEXT: s_cselect_b32 s0, 22, 33
+; GCN-NEXT: v_mov_b32_e32 v1, s0
+; GCN-NEXT: global_store_dword v0, v1, s[2:3]
+; GCN-NEXT: s_endpgm
+ %and = and i32 %arg, 2147483648
+ %cmp = icmp eq i32 %and, 0
+ %sel = select i1 %cmp, i32 22, i32 33
+ store i32 %sel, i32 addrspace(1)* %p
+ ret void
+}
+
+; FIXME: this should result in "s_bitcmp0_b64 $arg, 63" or "s_bitcmp0_b32 $arg.sub1, 31"
+define amdgpu_kernel void @if_masked_0x8000000000000000(i64 %arg, i32 addrspace(1)* %p) {
+; GCN-LABEL: if_masked_0x8000000000000000:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_mov_b32 s0, 0
+; GCN-NEXT: v_mov_b32_e32 v0, 0
+; GCN-NEXT: s_and_b32 s1, s1, 0x80000000
+; GCN-NEXT: s_cmp_eq_u64 s[0:1], 0
+; GCN-NEXT: s_cselect_b32 s0, 22, 33
+; GCN-NEXT: v_mov_b32_e32 v1, s0
+; GCN-NEXT: global_store_dword v0, v1, s[2:3]
+; GCN-NEXT: s_endpgm
+ %and = and i64 %arg, 9223372036854775808
+ %cmp = icmp eq i64 %and, 0
+ %sel = select i1 %cmp, i32 22, i32 33
+ store i32 %sel, i32 addrspace(1)* %p
+ ret void
+}
diff --git a/llvm/test/CodeGen/AMDGPU/optimize-compare.mir b/llvm/test/CodeGen/AMDGPU/optimize-compare.mir
index b77ab553d664..78d4afc6a0aa 100644
--- a/llvm/test/CodeGen/AMDGPU/optimize-compare.mir
+++ b/llvm/test/CodeGen/AMDGPU/optimize-compare.mir
@@ -1442,3 +1442,522 @@ body: |
S_ENDPGM 0
...
+
+---
+name: and_1024_cmp_eq_u32_1024
+body: |
+ ; GCN-LABEL: name: and_1024_cmp_eq_u32_1024
+ ; GCN: bb.0:
+ ; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GCN: S_BITCMP1_B32 killed [[COPY]], 10, implicit-def $scc
+ ; GCN: S_CBRANCH_SCC0 %bb.2, implicit $scc
+ ; GCN: S_BRANCH %bb.1
+ ; GCN: bb.1:
+ ; GCN: successors: %bb.2(0x80000000)
+ ; GCN: bb.2:
+ ; GCN: S_ENDPGM 0
+ bb.0:
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $sgpr0, $vgpr0_vgpr1
+
+ %0:sreg_32 = COPY $sgpr0
+ %1:sreg_32 = S_AND_B32 1024, killed %0, implicit-def dead $scc
+ S_CMP_EQ_U32 killed %1:sreg_32, 1024, implicit-def $scc
+ S_CBRANCH_SCC0 %bb.2, implicit $scc
+ S_BRANCH %bb.1
+
+ bb.1:
+ successors: %bb.2(0x80000000)
+
+ bb.2:
+ S_ENDPGM 0
+
+...
+
+---
+name: and_0x80000000_cmp_eq_u32_0x80000000
+body: |
+ ; GCN-LABEL: name: and_0x80000000_cmp_eq_u32_0x80000000
+ ; GCN: bb.0:
+ ; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GCN: S_BITCMP1_B32 killed [[COPY]], 31, implicit-def $scc
+ ; GCN: S_CBRANCH_SCC0 %bb.2, implicit $scc
+ ; GCN: S_BRANCH %bb.1
+ ; GCN: bb.1:
+ ; GCN: successors: %bb.2(0x80000000)
+ ; GCN: bb.2:
+ ; GCN: S_ENDPGM 0
+ bb.0:
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $sgpr0, $vgpr0_vgpr1
+
+ %0:sreg_32 = COPY $sgpr0
+ %1:sreg_32 = S_AND_B32 2147483648, killed %0, implicit-def dead $scc
+ S_CMP_EQ_U32 killed %1:sreg_32, 2147483648, implicit-def $scc
+ S_CBRANCH_SCC0 %bb.2, implicit $scc
+ S_BRANCH %bb.1
+
+ bb.1:
+ successors: %bb.2(0x80000000)
+
+ bb.2:
+ S_ENDPGM 0
+
+...
+
+---
+name: and_0x80000000_cmp_ge_u32_0x80000000
+body: |
+ ; GCN-LABEL: name: and_0x80000000_cmp_ge_u32_0x80000000
+ ; GCN: bb.0:
+ ; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GCN: S_BITCMP1_B32 killed [[COPY]], 31, implicit-def $scc
+ ; GCN: S_CBRANCH_SCC0 %bb.2, implicit $scc
+ ; GCN: S_BRANCH %bb.1
+ ; GCN: bb.1:
+ ; GCN: successors: %bb.2(0x80000000)
+ ; GCN: bb.2:
+ ; GCN: S_ENDPGM 0
+ bb.0:
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $sgpr0, $vgpr0_vgpr1
+
+ %0:sreg_32 = COPY $sgpr0
+ %1:sreg_32 = S_AND_B32 2147483648, killed %0, implicit-def dead $scc
+ S_CMP_GE_U32 killed %1:sreg_32, 2147483648, implicit-def $scc
+ S_CBRANCH_SCC0 %bb.2, implicit $scc
+ S_BRANCH %bb.1
+
+ bb.1:
+ successors: %bb.2(0x80000000)
+
+ bb.2:
+ S_ENDPGM 0
+
+...
+
+---
+name: and_0x80000000_cmp_ge_i32_0x80000000
+body: |
+ ; GCN-LABEL: name: and_0x80000000_cmp_ge_i32_0x80000000
+ ; GCN: bb.0:
+ ; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 2147483648, killed [[COPY]], implicit-def dead $scc
+ ; GCN: S_CMP_GE_I32 killed [[S_AND_B32_]], 2147483648, implicit-def $scc
+ ; GCN: S_CBRANCH_SCC0 %bb.2, implicit $scc
+ ; GCN: S_BRANCH %bb.1
+ ; GCN: bb.1:
+ ; GCN: successors: %bb.2(0x80000000)
+ ; GCN: bb.2:
+ ; GCN: S_ENDPGM 0
+ bb.0:
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $sgpr0, $vgpr0_vgpr1
+
+ %0:sreg_32 = COPY $sgpr0
+ %1:sreg_32 = S_AND_B32 2147483648, killed %0, implicit-def dead $scc
+ S_CMP_GE_I32 killed %1:sreg_32, 2147483648, implicit-def $scc
+ S_CBRANCH_SCC0 %bb.2, implicit $scc
+ S_BRANCH %bb.1
+
+ bb.1:
+ successors: %bb.2(0x80000000)
+
+ bb.2:
+ S_ENDPGM 0
+
+...
+
+---
+name: and_1024_cmp_ge_i32_1024
+body: |
+ ; GCN-LABEL: name: and_1024_cmp_ge_i32_1024
+ ; GCN: bb.0:
+ ; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GCN: S_BITCMP1_B32 killed [[COPY]], 10, implicit-def $scc
+ ; GCN: S_CBRANCH_SCC0 %bb.2, implicit $scc
+ ; GCN: S_BRANCH %bb.1
+ ; GCN: bb.1:
+ ; GCN: successors: %bb.2(0x80000000)
+ ; GCN: bb.2:
+ ; GCN: S_ENDPGM 0
+ bb.0:
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $sgpr0, $vgpr0_vgpr1
+
+ %0:sreg_32 = COPY $sgpr0
+ %1:sreg_32 = S_AND_B32 1024, killed %0, implicit-def dead $scc
+ S_CMP_GE_I32 killed %1:sreg_32, 1024, implicit-def $scc
+ S_CBRANCH_SCC0 %bb.2, implicit $scc
+ S_BRANCH %bb.1
+
+ bb.1:
+ successors: %bb.2(0x80000000)
+
+ bb.2:
+ S_ENDPGM 0
+
+...
+
+---
+name: and_0x80000000_cmp_lg_i32_0
+body: |
+ ; GCN-LABEL: name: and_0x80000000_cmp_lg_i32_0
+ ; GCN: bb.0:
+ ; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GCN: S_BITCMP1_B32 killed [[COPY]], 31, implicit-def $scc
+ ; GCN: S_CBRANCH_SCC0 %bb.2, implicit $scc
+ ; GCN: S_BRANCH %bb.1
+ ; GCN: bb.1:
+ ; GCN: successors: %bb.2(0x80000000)
+ ; GCN: bb.2:
+ ; GCN: S_ENDPGM 0
+ bb.0:
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $sgpr0, $vgpr0_vgpr1
+
+ %0:sreg_32 = COPY $sgpr0
+ %1:sreg_32 = S_AND_B32 2147483648, killed %0, implicit-def dead $scc
+ S_CMP_LG_I32 killed %1:sreg_32, 0, implicit-def $scc
+ S_CBRANCH_SCC0 %bb.2, implicit $scc
+ S_BRANCH %bb.1
+
+ bb.1:
+ successors: %bb.2(0x80000000)
+
+ bb.2:
+ S_ENDPGM 0
+
+...
+
+---
+name: and_0x80000000_cmp_gt_i32_0
+body: |
+ ; GCN-LABEL: name: and_0x80000000_cmp_gt_i32_0
+ ; GCN: bb.0:
+ ; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 2147483648, killed [[COPY]], implicit-def dead $scc
+ ; GCN: S_CMP_GT_I32 killed [[S_AND_B32_]], 0, implicit-def $scc
+ ; GCN: S_CBRANCH_SCC0 %bb.2, implicit $scc
+ ; GCN: S_BRANCH %bb.1
+ ; GCN: bb.1:
+ ; GCN: successors: %bb.2(0x80000000)
+ ; GCN: bb.2:
+ ; GCN: S_ENDPGM 0
+ bb.0:
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $sgpr0, $vgpr0_vgpr1
+
+ %0:sreg_32 = COPY $sgpr0
+ %1:sreg_32 = S_AND_B32 2147483648, killed %0, implicit-def dead $scc
+ S_CMP_GT_I32 killed %1:sreg_32, 0, implicit-def $scc
+ S_CBRANCH_SCC0 %bb.2, implicit $scc
+ S_BRANCH %bb.1
+
+ bb.1:
+ successors: %bb.2(0x80000000)
+
+ bb.2:
+ S_ENDPGM 0
+
+...
+
+---
+name: and_0x80000000_cmp_gt_u32_0
+body: |
+ ; GCN-LABEL: name: and_0x80000000_cmp_gt_u32_0
+ ; GCN: bb.0:
+ ; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GCN: S_BITCMP1_B32 killed [[COPY]], 31, implicit-def $scc
+ ; GCN: S_CBRANCH_SCC0 %bb.2, implicit $scc
+ ; GCN: S_BRANCH %bb.1
+ ; GCN: bb.1:
+ ; GCN: successors: %bb.2(0x80000000)
+ ; GCN: bb.2:
+ ; GCN: S_ENDPGM 0
+ bb.0:
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $sgpr0, $vgpr0_vgpr1
+
+ %0:sreg_32 = COPY $sgpr0
+ %1:sreg_32 = S_AND_B32 2147483648, killed %0, implicit-def dead $scc
+ S_CMP_GT_U32 killed %1:sreg_32, 0, implicit-def $scc
+ S_CBRANCH_SCC0 %bb.2, implicit $scc
+ S_BRANCH %bb.1
+
+ bb.1:
+ successors: %bb.2(0x80000000)
+
+ bb.2:
+ S_ENDPGM 0
+
+...
+
+---
+name: and_0x80000000_cmp_eq_u64_0x80000000
+body: |
+ ; GCN-LABEL: name: and_0x80000000_cmp_eq_u64_0x80000000
+ ; GCN: bb.0:
+ ; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
+ ; GCN: S_BITCMP1_B64 killed [[COPY]], 35, implicit-def $scc
+ ; GCN: S_CBRANCH_SCC0 %bb.2, implicit $scc
+ ; GCN: S_BRANCH %bb.1
+ ; GCN: bb.1:
+ ; GCN: successors: %bb.2(0x80000000)
+ ; GCN: bb.2:
+ ; GCN: S_ENDPGM 0
+ bb.0:
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $sgpr0_sgpr1, $vgpr0_vgpr1
+
+ %0:sreg_64 = COPY $sgpr0_sgpr1
+ %1:sreg_64 = S_AND_B64 34359738368, killed %0, implicit-def dead $scc
+ S_CMP_EQ_U64 killed %1:sreg_64, 34359738368, implicit-def $scc
+ S_CBRANCH_SCC0 %bb.2, implicit $scc
+ S_BRANCH %bb.1
+
+ bb.1:
+ successors: %bb.2(0x80000000)
+
+ bb.2:
+ S_ENDPGM 0
+
+...
+
+---
+name: and_0x8000000000000000_cmp_eq_u64_0x8000000000000000
+body: |
+ ; GCN-LABEL: name: and_0x8000000000000000_cmp_eq_u64_0x8000000000000000
+ ; GCN: bb.0:
+ ; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
+ ; GCN: S_BITCMP1_B64 killed [[COPY]], 63, implicit-def $scc
+ ; GCN: S_CBRANCH_SCC0 %bb.2, implicit $scc
+ ; GCN: S_BRANCH %bb.1
+ ; GCN: bb.1:
+ ; GCN: successors: %bb.2(0x80000000)
+ ; GCN: bb.2:
+ ; GCN: S_ENDPGM 0
+ bb.0:
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $sgpr0_sgpr1, $vgpr0_vgpr1
+
+ %0:sreg_64 = COPY $sgpr0_sgpr1
+ %1:sreg_64 = S_AND_B64 9223372036854775808, killed %0, implicit-def dead $scc
+ S_CMP_EQ_U64 killed %1:sreg_64, 9223372036854775808, implicit-def $scc
+ S_CBRANCH_SCC0 %bb.2, implicit $scc
+ S_BRANCH %bb.1
+
+ bb.1:
+ successors: %bb.2(0x80000000)
+
+ bb.2:
+ S_ENDPGM 0
+
+...
+
+---
+name: and_2_cmp_eq_u32_2_used_and
+body: |
+ ; GCN-LABEL: name: and_2_cmp_eq_u32_2_used_and
+ ; GCN: bb.0:
+ ; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 2, killed [[COPY]], implicit-def $scc
+ ; GCN: S_CBRANCH_SCC0 %bb.2, implicit $scc
+ ; GCN: S_BRANCH %bb.1
+ ; GCN: bb.1:
+ ; GCN: successors: %bb.2(0x80000000)
+ ; GCN: S_NOP 0, implicit [[S_AND_B32_]]
+ ; GCN: bb.2:
+ ; GCN: S_ENDPGM 0
+ bb.0:
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $sgpr0, $vgpr0_vgpr1
+
+ %0:sreg_32 = COPY $sgpr0
+ %1:sreg_32 = S_AND_B32 2, killed %0, implicit-def dead $scc
+ S_CMP_EQ_U32 killed %1:sreg_32, 2, implicit-def $scc
+ S_CBRANCH_SCC0 %bb.2, implicit $scc
+ S_BRANCH %bb.1
+
+ bb.1:
+ successors: %bb.2(0x80000000)
+
+ S_NOP 0, implicit %1
+
+ bb.2:
+ S_ENDPGM 0
+
+...
+
+---
+name: and_3_cmp_eq_u32_3
+body: |
+ ; GCN-LABEL: name: and_3_cmp_eq_u32_3
+ ; GCN: bb.0:
+ ; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 3, killed [[COPY]], implicit-def dead $scc
+ ; GCN: S_CMP_EQ_U32 killed [[S_AND_B32_]], 3, implicit-def $scc
+ ; GCN: S_CBRANCH_SCC0 %bb.2, implicit $scc
+ ; GCN: S_BRANCH %bb.1
+ ; GCN: bb.1:
+ ; GCN: successors: %bb.2(0x80000000)
+ ; GCN: bb.2:
+ ; GCN: S_ENDPGM 0
+ bb.0:
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $sgpr0, $vgpr0_vgpr1
+
+ %0:sreg_32 = COPY $sgpr0
+ %1:sreg_32 = S_AND_B32 3, killed %0, implicit-def dead $scc
+ S_CMP_EQ_U32 killed %1:sreg_32, 3, implicit-def $scc
+ S_CBRANCH_SCC0 %bb.2, implicit $scc
+ S_BRANCH %bb.1
+
+ bb.1:
+ successors: %bb.2(0x80000000)
+
+ bb.2:
+ S_ENDPGM 0
+
+...
+
+---
+name: and_3_cmp_lg_u32_0
+body: |
+ ; GCN-LABEL: name: and_3_cmp_lg_u32_0
+ ; GCN: bb.0:
+ ; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 3, killed [[COPY]], implicit-def dead $scc
+ ; GCN: S_CMP_LG_U32 killed [[S_AND_B32_]], 0, implicit-def $scc
+ ; GCN: S_CBRANCH_SCC0 %bb.2, implicit $scc
+ ; GCN: S_BRANCH %bb.1
+ ; GCN: bb.1:
+ ; GCN: successors: %bb.2(0x80000000)
+ ; GCN: bb.2:
+ ; GCN: S_ENDPGM 0
+ bb.0:
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $sgpr0, $vgpr0_vgpr1
+
+ %0:sreg_32 = COPY $sgpr0
+ %1:sreg_32 = S_AND_B32 3, killed %0, implicit-def dead $scc
+ S_CMP_LG_U32 killed %1:sreg_32, 0, implicit-def $scc
+ S_CBRANCH_SCC0 %bb.2, implicit $scc
+ S_BRANCH %bb.1
+
+ bb.1:
+ successors: %bb.2(0x80000000)
+
+ bb.2:
+ S_ENDPGM 0
+
+...
+
+---
+name: and_4_cmp_lg_u32_0
+body: |
+ ; GCN-LABEL: name: and_4_cmp_lg_u32_0
+ ; GCN: bb.0:
+ ; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GCN: S_BITCMP1_B32 killed [[COPY]], 2, implicit-def $scc
+ ; GCN: S_CBRANCH_SCC0 %bb.2, implicit $scc
+ ; GCN: S_BRANCH %bb.1
+ ; GCN: bb.1:
+ ; GCN: successors: %bb.2(0x80000000)
+ ; GCN: bb.2:
+ ; GCN: S_ENDPGM 0
+ bb.0:
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $sgpr0, $vgpr0_vgpr1
+
+ %0:sreg_32 = COPY $sgpr0
+ %1:sreg_32 = S_AND_B32 4, killed %0, implicit-def dead $scc
+ S_CMP_LG_U32 killed %1:sreg_32, 0, implicit-def $scc
+ S_CBRANCH_SCC0 %bb.2, implicit $scc
+ S_BRANCH %bb.1
+
+ bb.1:
+ successors: %bb.2(0x80000000)
+
+ bb.2:
+ S_ENDPGM 0
+
+...
+
+---
+name: and_0x80000000_cmp_eq_u32_0
+body: |
+ ; GCN-LABEL: name: and_0x80000000_cmp_eq_u32_0
+ ; GCN: bb.0:
+ ; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GCN: S_BITCMP0_B32 killed [[COPY]], 31, implicit-def $scc
+ ; GCN: S_CBRANCH_SCC0 %bb.2, implicit $scc
+ ; GCN: S_BRANCH %bb.1
+ ; GCN: bb.1:
+ ; GCN: successors: %bb.2(0x80000000)
+ ; GCN: bb.2:
+ ; GCN: S_ENDPGM 0
+ bb.0:
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $sgpr0, $vgpr0_vgpr1
+
+ %0:sreg_32 = COPY $sgpr0
+ %1:sreg_32 = S_AND_B32 2147483648, killed %0, implicit-def dead $scc
+ S_CMP_EQ_U32 killed %1:sreg_32, 0, implicit-def $scc
+ S_CBRANCH_SCC0 %bb.2, implicit $scc
+ S_BRANCH %bb.1
+
+ bb.1:
+ successors: %bb.2(0x80000000)
+
+ bb.2:
+ S_ENDPGM 0
+
+...
+
+---
+name: and_0x8000000000000000_cmp_lg_u64_0x8000000000000000
+body: |
+ ; GCN-LABEL: name: and_0x8000000000000000_cmp_lg_u64_0x8000000000000000
+ ; GCN: bb.0:
+ ; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
+ ; GCN: S_BITCMP0_B64 killed [[COPY]], 63, implicit-def $scc
+ ; GCN: S_CBRANCH_SCC0 %bb.2, implicit $scc
+ ; GCN: S_BRANCH %bb.1
+ ; GCN: bb.1:
+ ; GCN: successors: %bb.2(0x80000000)
+ ; GCN: bb.2:
+ ; GCN: S_ENDPGM 0
+ bb.0:
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $sgpr0_sgpr1, $vgpr0_vgpr1
+
+ %0:sreg_64 = COPY $sgpr0_sgpr1
+ %1:sreg_64 = S_AND_B64 9223372036854775808, killed %0, implicit-def dead $scc
+ S_CMP_LG_U64 killed %1:sreg_64, 9223372036854775808, implicit-def $scc
+ S_CBRANCH_SCC0 %bb.2, implicit $scc
+ S_BRANCH %bb.1
+
+ bb.1:
+ successors: %bb.2(0x80000000)
+
+ bb.2:
+ S_ENDPGM 0
+
+...
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