[PATCH] D107647: [PowerPC] MMA - Add __builtin_vsx_build_pair and __builtin_mma_build_acc builtins

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai requested changes to this revision.
nemanjai added a comment.
This revision now requires changes to proceed.

There are some questions to answer here before proceeding:

1. Why do we not get paired vector loads and stores in the back end test cases for either little or big endian and regardless of whether we use the old or new builtins/intrinsics?
2. Is the code generated the same as that for GCC when:
  - The inputs are all from registers
  - The inputs are all from memory
  - The inputs are a mix of memory and registers
3. What do execution tests show for both little endian and big endian targets? Namely, write execution test cases that do everything mentioned in 2. above for both sets of builtins and confirm:
  - The behaviour is the same both with GCC and Clang for both LE and BE
  - The behaviour for new builtins is the same on LE and BE with both GCC and Clang
  - The behaviour for old builtins is different on LE and BE with both GCC and Clang

I am requesting changes until these questions are adequately addressed.



================
Comment at: llvm/include/llvm/IR/IntrinsicsPowerPC.td:1442
 
+  def int_ppc_vsx_build_pair :
+        Intrinsic<[llvm_v256i1_ty],
----------------
I find the need for this rather surprising. The new builtins should do the exact same thing as the old builtins but with elements in reversed order. So why do we need new intrinsics? Can we not just call the old intrinsics in the front end codegen but with arguments in reversed order?


================
Comment at: llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll:73
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    vmr v3, v2
+; CHECK-BE-NEXT:    stxv v2, 16(r3)
----------------
This indicates some kind of problem. Why are we moving a value from `v2` to `v3` and then not using `v3`?


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  https://reviews.llvm.org/D107647/new/

https://reviews.llvm.org/D107647