[PATCH] D109074: [Codegen][TLI][X86] SimplifyMultipleUseDemandedBits(): 0'th vec subreg widening is free, try to perform it earlier

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri created this revision.
lebedev.ri added reviewers: RKSimon, craig.topper, spatel.
lebedev.ri added a project: LLVM.
Herald added subscribers: pengfei, hiraditya.
lebedev.ri requested review of this revision.

I believe, the profitability reasoning here is correct?
subreg is already located within the 0'th subreg of wider reg,
so if we have suvector insertion at index 0 into undef,
then it's always free do to?

After this, D109065 <https://reviews.llvm.org/D109065> finally avoids the regression in D108382 <https://reviews.llvm.org/D108382>.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D109074

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll
  llvm/test/CodeGen/X86/avg.ll
  llvm/test/CodeGen/X86/horizontal-sum.ll

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