[PATCH] D108973: [SLP][RISCV] Implement unsigned getMinVectorRegisterBitWidth() for RISCV

[Luke via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGa78dd726f46d: [SLP][RISCV] Implement unsigned getMinVectorRegisterBitWidth() for RISCV (authored by luke957).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108973/new/

https://reviews.llvm.org/D108973

Files:
  llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h


Index: llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -73,6 +73,10 @@
     llvm_unreachable("Unsupported register kind");
   }
 
+  unsigned getMinVectorRegisterBitWidth() const {
+    return ST->hasStdExtV() ? ST->getMinRVVVectorSizeInBits() : 0;
+  }
+
   InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
                                          const Value *Ptr, bool VariableMask,
                                          Align Alignment,


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