[PATCH] D108973: [SLP][RISCV] Implement unsigned getMinVectorRegisterBitWidth() for RISCV

[Luke via Phabricator via llvm-commits]

luke957 added a comment.

In D108973#2976094 <https://reviews.llvm.org/D108973#2976094>, @craig.topper wrote:

> In D108973#2976093 <https://reviews.llvm.org/D108973#2976093>, @luke957 wrote:
>
>> In D108973#2974682 <https://reviews.llvm.org/D108973#2974682>, @craig.topper wrote:
>>
>>> Tests?
>>
>> Em, I haven't got a proper test case for this. Without this methed being implemented, the mothed in super class will be called and got a return value of 128.
>>
>> In D108973#2974808 <https://reviews.llvm.org/D108973#2974808>, @craig.topper wrote:
>>
>>> Is this function just picking the minimum size of vector SLP will use? Do we want that to follow getRegisterBitWidth() or should it be allowed to be lower?
>>
>> Oh, I get your point. For RVV, we can use a vector registor fractionally, so minimum size of vector could be less than MinVectorRegisterBitWidth. But I'm not sure whether it is appropriate for a methed naming `getMinVectorRegisterBitWidth`.
>
> There was a vague suggestion about possibly adding a new getMinVectorizationBitWidth mentioned here https://reviews.llvm.org/D103925
>
> Anyway this patch is probably good as a starting point. LGTM

Thanks. I'll look into this patch.


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