[PATCH] D109008: [AMDGPU][NFC] Refactor AMDGPUCallingConv.td
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 31 11:38:46 PDT 2021
arsenm added inline comments.
================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td:147
+//===----------------------------------------------------------------------===//
+// Compute Calling Conventions
+//===----------------------------------------------------------------------===//
----------------
It's not entirely accurate since amdgpu_gfx will use the same masks
================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td:230
+
+def CSR_AMDGPU_AllVGPRs : RegMask<
+ (sequence "VGPR%u", 0, 255)
----------------
Probably shouldn't have the CSR prefix if it's just all registers
================
Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:352-353
case CallingConv::AMDGPU_Gfx:
return MF->getSubtarget<GCNSubtarget>().hasGFX90AInsts()
- ? CSR_AMDGPU_HighRegs_With_AGPRs_SaveList
- : CSR_AMDGPU_HighRegs_SaveList;
+ ? CSR_AMDGPU_GFX90AInsts_SaveList
+ : CSR_AMDGPU_SaveList;
----------------
Changing the convention based on the subtarget seems problematic. Do we really need to do this?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D109008/new/
https://reviews.llvm.org/D109008
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