[PATCH] D109008: [AMDGPU][NFC] Refactor AMDGPUCallingConv.td

[Scott Linder via Phabricator via llvm-commits]

scott.linder created this revision.
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Partition the file into "graphics", "compute", and "regmask" sections.

Remove unused CalleeSavedRegs defs CSR_AMDGPU_VGPRs_24_255 and
CSR_AMDGPU_VGPRs_32_255 which appear to be leftovers from old iterations
of the calling convention.

Rename CalleeSavedRegs defs to avoid being overly specific:

- CSR_AMDGPU_AGPRs_32_255 => CSR_AMDGPU_AGPRs
- CSR_AMDGPU_SGPRs_32_105 => CSR_AMDGPU_SGPRs
- CSR_AMDGPU_HighRegs => CSR_AMDGPU
- CSR_AMDGPU_HighRegs_With_AGPRs => CSR_AMDGPU_GFX90AInsts

Introduce a class RegMask to mark the cases where we use the
CalleeSavedRegs class purely as an expedient way to produce a mask.
Other targets also seem to do this, so a reasonable alternative is to
actually update table-gen to include a new class to do this explicitly,
but the current approach seems harmless so I opted to just make it more
explicit.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D109008

Files:
  llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
  llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
  llvm/test/CodeGen/AMDGPU/call-waw-waitcnt.mir
  llvm/test/CodeGen/AMDGPU/collapse-endcf2.mir
  llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir
  llvm/test/CodeGen/AMDGPU/fold-operands-remove-m0-redef.mir
  llvm/test/CodeGen/AMDGPU/greedy-alloc-fail-sgpr1024-spill.mir
  llvm/test/CodeGen/AMDGPU/limit-soft-clause-reg-pressure.mir
  llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
  llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir
  llvm/test/CodeGen/AMDGPU/splitkit-copy-bundle.mir
  llvm/test/CodeGen/AMDGPU/verify-gfx90a-aligned-vgprs.mir
  llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
  llvm/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir
  llvm/test/CodeGen/MIR/AMDGPU/stack-id-assert.mir

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