[PATCH] D109009: [AMDGPU] Update Call Convention docs for GFX90A

[Scott Linder via Phabricator via llvm-commits]

scott.linder created this revision.
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Document the CSR AGPRs for GFX90A.

Remove the TODO for gfx908, as the answer is that we don't mark any
AGPRs as callee-saved except for GFX90A, i.e. the docs as-is are correct
for gfx908.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D109009

Files:
  llvm/docs/AMDGPUUsage.rst


Index: llvm/docs/AMDGPUUsage.rst
===================================================================
--- llvm/docs/AMDGPUUsage.rst
+++ llvm/docs/AMDGPUUsage.rst
@@ -10835,6 +10835,7 @@
           registers are intermixed at regular intervals in order to keep a
           similar ratio independent of the number of allocated VGPRs.
 
+    * GFX90A: All AGPR registers except the clobbered registers AGPR0-31.
     * Lanes of all VGPRs that are inactive at the call site.
 
       For the AMDGPU backend, an inter-procedural register allocation (IPRA)
@@ -10850,8 +10851,6 @@
 
 .. TODO::
 
-  - On gfx908 are all ACC registers clobbered?
-
   - How are function results returned? The address of structured types is passed
     by reference, but what about other types?
 


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