[PATCH] D105799: [X86] Enable half type support in inline assembly constraints

[Pengfei Wang via Phabricator via llvm-commits]

pengfei added inline comments.


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Comment at: llvm/test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll:22
+; CHECK-STDERR: couldn't allocate output register for constraint 'x'
+define <32 x half> @mask_Yk_f16(i8 signext %msk, <32 x half> %x, <32 x half> %y) {
+entry:
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LuoYuanke wrote:
> Add more vector types (half, <8 x half>) to improve the coverage?
There will be many tests to meet the coverage, since we have the matrix {'v', 'x', 'Yz', ...} * 128/256/512. I checked we don't fully tested double either, I guess there might be no much value to do so since no difference among different FP types in SSE register classes.


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  https://reviews.llvm.org/D105799/new/

https://reviews.llvm.org/D105799