[PATCH] D108813: [RISCV] Implement CSR seccfg for spec Smepmp

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This revision implements CSR seccfg for RISCV according to the specification of version 0.9.4 <https://github.com/riscv/riscv-tee/blob/main/Smepmp/Smepmp.pdf>.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D108813

Files:
  llvm/lib/Target/RISCV/RISCVSystemOperands.td
  llvm/test/MC/RISCV/machine-csr-names.s
  llvm/test/MC/RISCV/rv32-machine-csr-names.s
  llvm/test/MC/RISCV/rv64-machine-csr-names.s


Index: llvm/test/MC/RISCV/rv64-machine-csr-names.s
===================================================================
--- llvm/test/MC/RISCV/rv64-machine-csr-names.s
+++ llvm/test/MC/RISCV/rv64-machine-csr-names.s
@@ -25,6 +25,13 @@
 # CHECK-INST-ALIAS: csrr t2, 931
 csrrs t2, 0x3A3, zero
 
+# mseccfgh
+# uimm12
+# CHECK-INST: csrrs t2, 1879, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x70,0x75]
+# CHECK-INST-ALIAS: csrr t2, 1879
+csrrs t2, 0x757, zero
+
 ######################################
 # Machine Counter and Timers
 ######################################
Index: llvm/test/MC/RISCV/rv32-machine-csr-names.s
===================================================================
--- llvm/test/MC/RISCV/rv32-machine-csr-names.s
+++ llvm/test/MC/RISCV/rv32-machine-csr-names.s
@@ -36,6 +36,20 @@
 # uimm12
 csrrs t2, 0x3A3, zero
 
+# mseccfgh
+# name
+# CHECK-INST: csrrs t1, mseccfgh, zero
+# CHECK-ENC:  encoding: [0x73,0x23,0x70,0x75]
+# CHECK-INST-ALIAS: csrr t1, mseccfgh
+# uimm12
+# CHECK-INST: csrrs t2, mseccfgh, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x70,0x75]
+# CHECK-INST-ALIAS: csrr t2, mseccfgh
+# name
+csrrs t1, mseccfgh, zero
+# uimm12
+csrrs t2, 0x757, zero
+
 ######################################
 # Machine Counter and Timers
 ######################################
Index: llvm/test/MC/RISCV/machine-csr-names.s
===================================================================
--- llvm/test/MC/RISCV/machine-csr-names.s
+++ llvm/test/MC/RISCV/machine-csr-names.s
@@ -276,6 +276,19 @@
 # uimm12
 csrrs t2, 0x3A2, zero
 
+# mseccfg
+# name
+# CHECK-INST: csrrs t1, mseccfg, zero
+# CHECK-ENC:  encoding: [0x73,0x23,0x70,0x74]
+# CHECK-INST-ALIAS: csrr t1, mseccfg
+# uimm12
+# CHECK-INST: csrrs t2, mseccfg, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x70,0x74]
+# CHECK-INST-ALIAS: csrr t2, mseccfg
+# name
+csrrs t1, mseccfg, zero
+# uimm12
+csrrs t2, 0x747, zero
 
 ######################################
 # Machine Counter and Timers
Index: llvm/lib/Target/RISCV/RISCVSystemOperands.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -251,6 +251,9 @@
 def : SysReg<"pmpaddr14", 0x3BE>;
 def : SysReg<"pmpaddr15", 0x3BF>;
 
+def : SysReg<"mseccfg", 0x747>;
+let isRV32Only = 1 in
+def : SysReg<"mseccfgh", 0x757>;
 
 //===--------------------------
 // Machine Counter and Timers


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