[PATCH] D108663: [RISCV] Insert a sext_inreg when type legalizing i32 shl by constant on RV64.

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 368916.
craig.topper added a comment.

Rebase on top of bitreverse changes from D108738 <https://reviews.llvm.org/D108738>


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108663/new/

https://reviews.llvm.org/D108663

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  llvm/test/CodeGen/RISCV/alu32.ll
  llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
  llvm/test/CodeGen/RISCV/copysign-casts.ll
  llvm/test/CodeGen/RISCV/mul.ll
  llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
  llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll
  llvm/test/CodeGen/RISCV/rv64zbb.ll
  llvm/test/CodeGen/RISCV/rv64zbp.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D108663.368916.patch
Type: text/x-patch
Size: 30532 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210826/7a589dff/attachment.bin>