[PATCH] D108706: [AArch64][SVE] Optimize ptrue predicate pattern with known sve register width.

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:3836-3839
+  const auto &Subtarget =
+      static_cast<const AArch64Subtarget &>(DAG.getSubtarget());
+  unsigned MinSVESize = Subtarget.getMinSVEVectorSizeInBits();
+  unsigned MaxSVESize = Subtarget.getMaxSVEVectorSizeInBits();
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junparser wrote:
> paulwalker-arm wrote:
> > There should already be placeholder for this logic.  If you look at `getPredicateForFixedLengthVector` you'll see a TODO comment.
> I uniformly use getPTrue for all of the creation of ptrue in NFC patch, then we can even handle sve.ptrue intrinsic which we have seen in some cases. 
This doesn't really change my mind. `getPTrue` exists as purely a convenience routine, which I think should always emit exactly what the caller asks for. The design for fixed length code generation already has a placeholder for this logic.

Which just leaves the intrinsic case. This is best handled explicitly, either when lowering the intrinsic or perhaps even as an instcombine which can open up more optimisation opportunities.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108706/new/

https://reviews.llvm.org/D108706