[PATCH] D108694: [RISCV] Add the zvl extension according to the v1.0-rc1 spec

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng added inline comments.


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Comment at: llvm/lib/Support/RISCVISAInfo.cpp:72
+    {"zvl512b", RISCVExtensionVersion{0, 10}},
+    {"zvl1024b", RISCVExtensionVersion{0, 10}},
 
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Although the table in vector spec only list `zvl32b`~`zvl1024b`, but there is note say `Longer vector length extensions should follow the same pattern.`[1], so I would suggest let enumerate to 65536, the unbound of VLEN[2],  


[1] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#181-zvl-minimum-vector-length-standard-extensions
[2] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#2-implementation-defined-constant-parameters


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Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.cpp:134
          "maximum!");
+  assert(RVVVectorBitsMin >= ZvlLen &&
+         "Minimum V extension vector length should be at least the length "
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I guess this should be more than an assertion? but I am not sure does it make sense to emit error or warning here? or just silently return `ZvlLen` if `RVVVectorBitsMin` is less than `ZvlLen`.


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