[PATCH] D108675: [RISCV] Add a PreprocessISelDAG peephole for (i64 (srl (and X, C)))

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

Maybe a better fix is to just move the and after the shift in DAG combine. That would guarantee bit 31 moves right at least 1 bit. That would be enough to guarantee it goes from a uimm32 constant to a simm32 constant.


Repository:
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  https://reviews.llvm.org/D108675/new/

https://reviews.llvm.org/D108675