[PATCH] D108675: [RISCV] Add a PreprocessISelDAG peephole for (i64 (srl (and X, C)))

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Aug 24 16:58:08 PDT 2021


craig.topper created this revision.
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For cases where C is a uimm32 but not simm32. We can split the and
into (and (and X, sext32(C), 0xffffffff)). The outer and will be
selected with the srl to form srliw. The inner and will be selected
as an AND instruction with a sext32(C) materialized separately.

This prevents regressions from D108663 <https://reviews.llvm.org/D108663>, but is helpful on its own.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D108675

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/test/CodeGen/RISCV/copysign-casts.ll
  llvm/test/CodeGen/RISCV/rv64zbp.ll

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