[PATCH] D108663: [RISCV] Insert a sext_inreg when type legalizing i32 shl by constant on RV64.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoB.td:1140
 let Predicates = [HasStdExtZbp, IsRV64] in {
 def : Pat<(i64 (sext_inreg (or (shl GPR:$rs2, (i64 16)),
                                (and GPR:$rs1, 0x000000000000FFFF)),
----------------
jrtc27 wrote:
> Does this pattern still get generated? If so it's a shame one isn't canonicalised to the other :(
I think we would still generate it for this

```
int foo(unsigned long long x, unsigned long long y) {
  return (x << 16) | (y & 0xffff);
}
```

Type legalization doesn't get involved since x and y are i64. A sign extend will be introduced for the result due to ABI.

In general, we should be pushing sext to the inputs of and/or/xor looking for locations that would make them free. This case could be done with a simple peephole. More complex cases could require looking back through multiple logic ops which could become computationally expensive.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108663/new/

https://reviews.llvm.org/D108663