[PATCH] D107160: [AArch64] Do not emit an extra zero-extend for i1 argument

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

This turned out much messier than I was hoping for...

I guess we have the following possibilities:

1. Go back to the original patch.
2. Go with something like this approach, maybe with a few small cleanups.
3. Try to use target-specific nodes to dodge the legalization issues.  Instead of using the target-independent nodes, introduce AArch64ISD::AssertZextBool/AArch64::ZERO_EXTEND_BOOL which have an i32 argument/result, and then DAGCombine them away after type legalization cleans up all the extend/truncate ops which make this harder to analyze.  Maybe more code, but easier to understand the implications, I think.

You might want to add a testcase where the call isn't in the entry block; I think maybe the original patch handles this?



================
Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:3889
+          // clear that the condition only checks for a single bit.
+          SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Op0);
+          return DAG.getSetCC(dl, VT, Trunc,
----------------
You can't unconditionally truncate to i1 here, I think; this might be after type legalization.


Repository:
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  https://reviews.llvm.org/D107160/new/

https://reviews.llvm.org/D107160