[PATCH] D107160: [AArch64] Do not emit an extra zero-extend for i1 argument

[Andrew Savonichev via Phabricator via llvm-commits]

asavonic updated this revision to Diff 368054.
asavonic edited the summary of this revision.
asavonic added a comment.

Used an AssertZExt to keep information about zero-extended low bits.
There were a number of places where the compiler failed to optimize this correctly (found by LIT tests), so I fixed them as well.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107160/new/

https://reviews.llvm.org/D107160

Files:
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
  llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
  llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-signext.ll
  llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll
  llvm/test/CodeGen/AArch64/arm64-aapcs.ll
  llvm/test/CodeGen/AArch64/i1-contents.ll
  llvm/test/CodeGen/AArch64/select_const.ll

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