[llvm] af8e09d - [GlobalISel] Add G_LLROUND
Jessica Paquette via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 20 14:17:49 PDT 2021
Author: Jessica Paquette
Date: 2021-08-20T14:07:21-07:00
New Revision: af8e09d4bbe8e8034f288c4d1c728323823c7e71
URL: https://github.com/llvm/llvm-project/commit/af8e09d4bbe8e8034f288c4d1c728323823c7e71
DIFF: https://github.com/llvm/llvm-project/commit/af8e09d4bbe8e8034f288c4d1c728323823c7e71.diff
LOG: [GlobalISel] Add G_LLROUND
Basically the same as G_LROUND. Handles the llvm.llround family of intrinsics.
Also add a helper function to the MachineVerifier for checking if all of the
(virtual register) operands of an instruction are scalars. Seems like a useful
thing to have.
Differential Revision: https://reviews.llvm.org/D108429
Added:
llvm/test/MachineVerifier/test_g_llround.mir
Modified:
llvm/docs/GlobalISel/GenericOpcode.rst
llvm/include/llvm/Support/TargetOpcodes.def
llvm/include/llvm/Target/GenericOpcodes.td
llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
llvm/lib/CodeGen/MachineVerifier.cpp
llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
llvm/test/MachineVerifier/test_g_lround.mir
Removed:
################################################################################
diff --git a/llvm/docs/GlobalISel/GenericOpcode.rst b/llvm/docs/GlobalISel/GenericOpcode.rst
index e08e59e1dd2b4..6941aec2290cf 100644
--- a/llvm/docs/GlobalISel/GenericOpcode.rst
+++ b/llvm/docs/GlobalISel/GenericOpcode.rst
@@ -573,8 +573,8 @@ G_INTRINSIC_ROUND
Returns the operand rounded to the nearest integer.
-G_LROUND
-^^^^^^^^
+G_LROUND, G_LLROUND
+^^^^^^^^^^^^^^^^^^^
Returns the source operand rounded to the nearest integer with ties away from
zero.
@@ -584,7 +584,7 @@ See the LLVM LangRef entry on '``llvm.lround.*'`` for details on behaviour.
.. code-block:: none
%rounded_32:_(s32) = G_LROUND %round_me:_(s64)
- %rounded_64:_(s64) = G_LROUND %round_me:_(s64)
+ %rounded_64:_(s64) = G_LLROUND %round_me:_(s64)
Vector Specific Operations
--------------------------
diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def
index 99603b914a264..b33c4ae1a888c 100644
--- a/llvm/include/llvm/Support/TargetOpcodes.def
+++ b/llvm/include/llvm/Support/TargetOpcodes.def
@@ -653,6 +653,7 @@ HANDLE_TARGET_OPCODE(G_UMAX)
HANDLE_TARGET_OPCODE(G_ABS)
HANDLE_TARGET_OPCODE(G_LROUND)
+HANDLE_TARGET_OPCODE(G_LLROUND)
/// Generic BRANCH instruction. This is an unconditional branch.
HANDLE_TARGET_OPCODE(G_BR)
diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td
index 28aecd40a7cf0..58140cb71dc80 100644
--- a/llvm/include/llvm/Target/GenericOpcodes.td
+++ b/llvm/include/llvm/Target/GenericOpcodes.td
@@ -238,6 +238,12 @@ def G_LROUND: GenericInstruction {
let hasSideEffects = false;
}
+def G_LLROUND: GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type1:$src);
+ let hasSideEffects = false;
+}
+
//------------------------------------------------------------------------------
// Binary ops.
//------------------------------------------------------------------------------
diff --git a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
index 647b694b1ba1c..12eee24b578f8 100644
--- a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
+++ b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
@@ -145,6 +145,7 @@ def : GINodeEquiv<G_READCYCLECOUNTER, readcyclecounter>;
def : GINodeEquiv<G_ROTR, rotr>;
def : GINodeEquiv<G_ROTL, rotl>;
def : GINodeEquiv<G_LROUND, lround>;
+def : GINodeEquiv<G_LLROUND, llround>;
def : GINodeEquiv<G_STRICT_FADD, strict_fadd>;
def : GINodeEquiv<G_STRICT_FSUB, strict_fsub>;
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index b15e4881f807d..93942cdd0e4de 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -210,6 +210,11 @@ namespace {
void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
void visitMachineBundleBefore(const MachineInstr *MI);
+ /// Verify that all of \p MI's virtual register operands are scalars.
+ /// \returns True if all virtual register operands are scalar. False
+ /// otherwise.
+ bool verifyAllRegOpsScalar(const MachineInstr &MI,
+ const MachineRegisterInfo &MRI);
bool verifyVectorElementMatch(LLT Ty0, LLT Ty1, const MachineInstr *MI);
void verifyPreISelGenericInstruction(const MachineInstr *MI);
void visitMachineInstrBefore(const MachineInstr *MI);
@@ -849,6 +854,21 @@ void MachineVerifier::verifyInlineAsm(const MachineInstr *MI) {
}
}
+bool MachineVerifier::verifyAllRegOpsScalar(const MachineInstr &MI,
+ const MachineRegisterInfo &MRI) {
+ if (none_of(MI.explicit_operands(), [&MRI](const MachineOperand &Op) {
+ if (!Op.isReg())
+ return false;
+ const auto Reg = Op.getReg();
+ if (Reg.isPhysical())
+ return false;
+ return !MRI.getType(Reg).isScalar();
+ }))
+ return true;
+ report("All register operands must have scalar types", &MI);
+ return false;
+}
+
/// Check that types are consistent when two operands need to have the same
/// number of vector elements.
/// \return true if the types are valid.
@@ -1614,14 +1634,11 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
}
break;
}
-
+ case TargetOpcode::G_LLROUND:
case TargetOpcode::G_LROUND: {
- if (!MRI->getType(MI->getOperand(0).getReg()).isScalar() ||
- !MRI->getType(MI->getOperand(1).getReg()).isScalar())
- report("lround only supports scalars", MI);
+ verifyAllRegOpsScalar(*MI, *MRI);
break;
}
-
default:
break;
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
index 3bf999e7d82ab..1de81c3a3dcff 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
@@ -529,6 +529,9 @@
# DEBUG-NEXT: G_LROUND (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: G_LLROUND (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
+# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
# DEBUG-NEXT: G_BR (opcode {{[0-9]+}}): 0 type indices, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
diff --git a/llvm/test/MachineVerifier/test_g_llround.mir b/llvm/test/MachineVerifier/test_g_llround.mir
new file mode 100644
index 0000000000000..3e43d3408e8d9
--- /dev/null
+++ b/llvm/test/MachineVerifier/test_g_llround.mir
@@ -0,0 +1,23 @@
+#RUN: not --crash llc -march=aarch64 -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# REQUIRES: aarch64-registered-target
+
+---
+name: test_llround
+legalized: true
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+liveins:
+body: |
+ bb.0:
+ liveins: $x0, $q0
+ %ptr:_(p0) = COPY $x0
+ %vector:_(<2 x s64>) = COPY $q0
+
+ ; CHECK: Bad machine code: All register operands must have scalar types
+ ; CHECK: instruction: %no_ptrs:_(s64) = G_LROUND %ptr:_(p0)
+ %no_ptrs:_(s64) = G_LROUND %ptr:_(p0)
+
+ ; CHECK: Bad machine code: All register operands must have scalar types
+ ; CHECK: instruction: %no_vectors:_(s64) = G_LROUND %vector:_(<2 x s64>)
+ %no_vectors:_(s64) = G_LROUND %vector:_(<2 x s64>)
diff --git a/llvm/test/MachineVerifier/test_g_lround.mir b/llvm/test/MachineVerifier/test_g_lround.mir
index 2f999b4823161..259ffc05d404f 100644
--- a/llvm/test/MachineVerifier/test_g_lround.mir
+++ b/llvm/test/MachineVerifier/test_g_lround.mir
@@ -14,10 +14,10 @@ body: |
%ptr:_(p0) = COPY $x0
%vector:_(<2 x s64>) = COPY $q0
- ; CHECK: Bad machine code: lround only supports scalars
+ ; CHECK: Bad machine code: All register operands must have scalar types
; CHECK: instruction: %no_ptrs:_(s32) = G_LROUND %ptr:_(p0)
%no_ptrs:_(s32) = G_LROUND %ptr:_(p0)
- ; CHECK: Bad machine code: lround only supports scalars
+ ; CHECK: Bad machine code: All register operands must have scalar types
; CHECK: instruction: %no_vectors:_(s32) = G_LROUND %vector:_(<2 x s64>)
%no_vectors:_(s32) = G_LROUND %vector:_(<2 x s64>)
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