[PATCH] D106653: [LoopVectorize][AArch64] Enable ordered reductions by default for AArch64

[Florian Hahn via Phabricator via llvm-commits]

fhahn added a comment.

In D106653#2957702 <https://reviews.llvm.org/D106653#2957702>, @pcc wrote:

> Hi David, it looks like this change caused an assertion failure. Can you please take a look?
>
>   > cat test.i
>   int a;
>   double b, c;
>   void d() {
>     for (; a; a++) {
>       b += c;
>       c = a;
>     }
>   }
>   > clang -O2 test.i --target=aarch64-linux
>   clang: ../llvm/lib/Transforms/Vectorize/VPlanValue.h:186: llvm::Value *llvm::VPValue::getLiveInIRValue(): Assertion `!getDef() && "VPValue is not a live-in; it is defined by a VPDef inside a VPlan"' failed.

Thanks for the report! I have a suspicion of what may be going wrong here. I'll revert the patch while I take a look.


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  https://reviews.llvm.org/D106653/new/

https://reviews.llvm.org/D106653