[PATCH] D106653: [LoopVectorize][AArch64] Enable ordered reductions by default for AArch64

[Peter Collingbourne via Phabricator via llvm-commits]

pcc added a comment.

Hi David, it looks like this change caused an assertion failure. Can you please take a look?

  > cat test.i
  int a;
  double b, c;
  void d() {
    for (; a; a++) {
      b += c;
      c = a;
    }
  }
  > clang -O2 test.i --target=aarch64-linux
  clang: ../llvm/lib/Transforms/Vectorize/VPlanValue.h:186: llvm::Value *llvm::VPValue::getLiveInIRValue(): Assertion `!getDef() && "VPValue is not a live-in; it is defined by a VPDef inside a VPlan"' failed.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106653/new/

https://reviews.llvm.org/D106653