[PATCH] D108279: [AArch64][SME] Fix v8.6a bf16 NEON instruction predication

[Cullen Rhodes via Phabricator via llvm-commits]

c-rhodes created this revision.
c-rhodes added reviewers: paulwalker-arm, david-arm, stuij.
Herald added subscribers: ctetreau, hiraditya, kristof.beyls.
c-rhodes requested review of this revision.
Herald added a project: LLVM.

In streaming mode on SME targets only the scalar BFCVT armv8.6-a
instruction is legal, predicate the illegal instructions on NEON to
disable them in streaming mode (see D107902 <https://reviews.llvm.org/D107902>). BFCVT is predicated on
HasNEONorStreamingSVE.

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2021-06/SIMD-FP-Instructions


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D108279

Files:
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/MC/AArch64/SME/streaming-mode-neon-bf16.s
  llvm/test/MC/AArch64/SME/streaming-mode-neon-negative.s


Index: llvm/test/MC/AArch64/SME/streaming-mode-neon-negative.s
===================================================================
--- llvm/test/MC/AArch64/SME/streaming-mode-neon-negative.s
+++ llvm/test/MC/AArch64/SME/streaming-mode-neon-negative.s
@@ -1,4 +1,5 @@
 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+streaming-sve 2>&1 < %s| FileCheck %s
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+streaming-sve,+bf16 2>&1 < %s| FileCheck %s --check-prefix=CHECK-BF16
 
 // ------------------------------------------------------------------------- //
 // Check non-zero index is illegal in streaming mode
@@ -162,3 +163,11 @@
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: neon
 // CHECK-NEXT: fabd s0, s1, s2
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Check non-scalar v8.6a BFloat16 instructions are illegal in streaming mode
+
+bfcvtn v5.4h, v5.4s
+// CHECK-BF16: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: neon
+// CHECK-BF16-NEXT: bfcvtn v5.4h, v5.4s
+// CHECK-BF16-NOT: [[@LINE-1]]:{{[0-9]+}}:
Index: llvm/test/MC/AArch64/SME/streaming-mode-neon-bf16.s
===================================================================
--- /dev/null
+++ llvm/test/MC/AArch64/SME/streaming-mode-neon-bf16.s
@@ -0,0 +1,16 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+streaming-sve,+bf16 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=-neon < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+streaming-sve,+bf16 < %s \
+// RUN:        | llvm-objdump --mattr=+bf16 -d - | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+streaming-sve,+bf16 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+streaming-sve,+bf16 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+bfcvt h5, s3
+// CHECK-INST: bfcvt h5, s3
+// CHECK-ENCODING: [0x65,0x40,0x63,0x1e]
+// CHECK-ERROR: instruction requires: bf16
Index: llvm/lib/Target/AArch64/AArch64InstrInfo.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -873,7 +873,7 @@
 }
 
 // ARMv8.6-A BFloat
-let Predicates = [HasBF16] in {
+let Predicates = [HasNEON, HasBF16] in {
 defm BFDOT       : SIMDThreeSameVectorBFDot<1, "bfdot">;
 defm BF16DOTlane : SIMDThreeSameVectorBF16DotI<0, "bfdot">;
 def BFMMLA       : SIMDThreeSameVectorBF16MatrixMul<"bfmmla">;
@@ -883,7 +883,6 @@
 def BFMLALTIdx   : SIMDBF16MLALIndex<1, "bfmlalt", int_aarch64_neon_bfmlalt>;
 def BFCVTN       : SIMD_BFCVTN;
 def BFCVTN2      : SIMD_BFCVTN2;
-def BFCVT        : BF16ToSinglePrecision<"bfcvt">;
 
 // Vector-scalar BFDOT:
 // The second source operand of the 64-bit variant of BF16DOTlane is a 128-bit
@@ -903,6 +902,10 @@
                              VectorIndexS:$idx)>;
 }
 
+let Predicates = [HasNEONorStreamingSVE, HasBF16] in {
+def BFCVT : BF16ToSinglePrecision<"bfcvt">;
+}
+
 // ARMv8.6A AArch64 matrix multiplication
 let Predicates = [HasMatMulInt8] in {
 def  SMMLA : SIMDThreeSameVectorMatMul<0, 0, "smmla", int_aarch64_neon_smmla>;


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