[llvm] 8f8f926 - [Test][AggressiveInstCombine] Add test for shifts
Anton Afanasyev via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 17 02:40:41 PDT 2021
Author: Anton Afanasyev
Date: 2021-08-17T12:39:53+03:00
New Revision: 8f8f9260a95f784e8c4620d652986724ac1b88df
URL: https://github.com/llvm/llvm-project/commit/8f8f9260a95f784e8c4620d652986724ac1b88df
DIFF: https://github.com/llvm/llvm-project/commit/8f8f9260a95f784e8c4620d652986724ac1b88df.diff
LOG: [Test][AggressiveInstCombine] Add test for shifts
Precommit test for D107766/D108091. Also move fixed test for PR50555
from SLPVectorizer/X86/ to PhaseOrdering/X86/ subdirectory.
Added:
llvm/test/Transforms/AggressiveInstCombine/trunc_shifts.ll
llvm/test/Transforms/PhaseOrdering/X86/pr50555.ll
Modified:
Removed:
llvm/test/Transforms/SLPVectorizer/X86/pr50555.ll
################################################################################
diff --git a/llvm/test/Transforms/AggressiveInstCombine/trunc_shifts.ll b/llvm/test/Transforms/AggressiveInstCombine/trunc_shifts.ll
new file mode 100644
index 0000000000000..67d78293564e7
--- /dev/null
+++ b/llvm/test/Transforms/AggressiveInstCombine/trunc_shifts.ll
@@ -0,0 +1,362 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -aggressive-instcombine -S | FileCheck %s
+
+define i16 @shl_1(i8 %x) {
+; CHECK-LABEL: @shl_1(
+; CHECK-NEXT: [[ZEXT:%.*]] = zext i8 [[X:%.*]] to i32
+; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[ZEXT]], 1
+; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[SHL]] to i16
+; CHECK-NEXT: ret i16 [[TRUNC]]
+;
+ %zext = zext i8 %x to i32
+ %shl = shl i32 %zext, 1
+ %trunc = trunc i32 %shl to i16
+ ret i16 %trunc
+}
+
+define i16 @shl_15(i8 %x) {
+; CHECK-LABEL: @shl_15(
+; CHECK-NEXT: [[ZEXT:%.*]] = zext i8 [[X:%.*]] to i32
+; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[ZEXT]], 15
+; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[SHL]] to i16
+; CHECK-NEXT: ret i16 [[TRUNC]]
+;
+ %zext = zext i8 %x to i32
+ %shl = shl i32 %zext, 15
+ %trunc = trunc i32 %shl to i16
+ ret i16 %trunc
+}
+
+; Negative test - shift amount isn't less than target bitwidth
+
+define i16 @shl_16(i8 %x) {
+; CHECK-LABEL: @shl_16(
+; CHECK-NEXT: [[ZEXT:%.*]] = zext i8 [[X:%.*]] to i32
+; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[ZEXT]], 16
+; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[SHL]] to i16
+; CHECK-NEXT: ret i16 [[TRUNC]]
+;
+ %zext = zext i8 %x to i32
+ %shl = shl i32 %zext, 16
+ %trunc = trunc i32 %shl to i16
+ ret i16 %trunc
+}
+
+; Negative test -- variable shift amount
+
+define i16 @shl_var_shift_amount(i8 %x, i8 %y) {
+; CHECK-LABEL: @shl_var_shift_amount(
+; CHECK-NEXT: [[ZEXT_X:%.*]] = zext i8 [[X:%.*]] to i32
+; CHECK-NEXT: [[ZEXT_Y:%.*]] = zext i8 [[Y:%.*]] to i32
+; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[ZEXT_X]], [[ZEXT_Y]]
+; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[SHL]] to i16
+; CHECK-NEXT: ret i16 [[TRUNC]]
+;
+ %zext.x = zext i8 %x to i32
+ %zext.y = zext i8 %y to i32
+ %shl = shl i32 %zext.x, %zext.y
+ %trunc = trunc i32 %shl to i16
+ ret i16 %trunc
+}
+
+define i16 @shl_var_bounded_shift_amount(i8 %x, i8 %y) {
+; CHECK-LABEL: @shl_var_bounded_shift_amount(
+; CHECK-NEXT: [[ZEXT_X:%.*]] = zext i8 [[X:%.*]] to i32
+; CHECK-NEXT: [[ZEXT_Y:%.*]] = zext i8 [[Y:%.*]] to i32
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[ZEXT_Y]], 15
+; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[ZEXT_X]], [[AND]]
+; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[SHL]] to i16
+; CHECK-NEXT: ret i16 [[TRUNC]]
+;
+ %zext.x = zext i8 %x to i32
+ %zext.y = zext i8 %y to i32
+ %and = and i32 %zext.y, 15
+ %shl = shl i32 %zext.x, %and
+ %trunc = trunc i32 %shl to i16
+ ret i16 %trunc
+}
+
+define <2 x i16> @shl_vector(<2 x i8> %x) {
+; CHECK-LABEL: @shl_vector(
+; CHECK-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i32>
+; CHECK-NEXT: [[S:%.*]] = shl <2 x i32> [[Z]], <i32 4, i32 10>
+; CHECK-NEXT: [[T:%.*]] = trunc <2 x i32> [[S]] to <2 x i16>
+; CHECK-NEXT: ret <2 x i16> [[T]]
+;
+ %z = zext <2 x i8> %x to <2 x i32>
+ %s = shl <2 x i32> %z, <i32 4, i32 10>
+ %t = trunc <2 x i32> %s to <2 x i16>
+ ret <2 x i16> %t
+}
+
+; Negative test - can only fold to <2 x i16>, requiring new vector type
+
+define <2 x i8> @shl_vector_no_new_vector_type(<2 x i8> %x) {
+; CHECK-LABEL: @shl_vector_no_new_vector_type(
+; CHECK-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i32>
+; CHECK-NEXT: [[S:%.*]] = shl <2 x i32> [[Z]], <i32 4, i32 10>
+; CHECK-NEXT: [[T:%.*]] = trunc <2 x i32> [[S]] to <2 x i8>
+; CHECK-NEXT: ret <2 x i8> [[T]]
+;
+ %z = zext <2 x i8> %x to <2 x i32>
+ %s = shl <2 x i32> %z, <i32 4, i32 10>
+ %t = trunc <2 x i32> %s to <2 x i8>
+ ret <2 x i8> %t
+}
+
+; Negative test
+
+define <2 x i16> @shl_vector_large_shift_amount(<2 x i8> %x) {
+; CHECK-LABEL: @shl_vector_large_shift_amount(
+; CHECK-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i32>
+; CHECK-NEXT: [[S:%.*]] = shl <2 x i32> [[Z]], <i32 16, i32 5>
+; CHECK-NEXT: [[T:%.*]] = trunc <2 x i32> [[S]] to <2 x i16>
+; CHECK-NEXT: ret <2 x i16> [[T]]
+;
+ %z = zext <2 x i8> %x to <2 x i32>
+ %s = shl <2 x i32> %z, <i32 16, i32 5>
+ %t = trunc <2 x i32> %s to <2 x i16>
+ ret <2 x i16> %t
+}
+
+define i16 @shl_nuw(i8 %x) {
+; CHECK-LABEL: @shl_nuw(
+; CHECK-NEXT: [[Z:%.*]] = zext i8 [[X:%.*]] to i32
+; CHECK-NEXT: [[S:%.*]] = shl nuw i32 [[Z]], 15
+; CHECK-NEXT: [[T:%.*]] = trunc i32 [[S]] to i16
+; CHECK-NEXT: ret i16 [[T]]
+;
+ %z = zext i8 %x to i32
+ %s = shl nuw i32 %z, 15
+ %t = trunc i32 %s to i16
+ ret i16 %t
+}
+
+define i16 @shl_nsw(i8 %x) {
+; CHECK-LABEL: @shl_nsw(
+; CHECK-NEXT: [[Z:%.*]] = zext i8 [[X:%.*]] to i32
+; CHECK-NEXT: [[S:%.*]] = shl nsw i32 [[Z]], 15
+; CHECK-NEXT: [[T:%.*]] = trunc i32 [[S]] to i16
+; CHECK-NEXT: ret i16 [[T]]
+;
+ %z = zext i8 %x to i32
+ %s = shl nsw i32 %z, 15
+ %t = trunc i32 %s to i16
+ ret i16 %t
+}
+
+define i16 @lshr_15(i16 %x) {
+; CHECK-LABEL: @lshr_15(
+; CHECK-NEXT: [[ZEXT:%.*]] = zext i16 [[X:%.*]] to i32
+; CHECK-NEXT: [[LSHR:%.*]] = lshr i32 [[ZEXT]], 15
+; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[LSHR]] to i16
+; CHECK-NEXT: ret i16 [[TRUNC]]
+;
+ %zext = zext i16 %x to i32
+ %lshr = lshr i32 %zext, 15
+ %trunc = trunc i32 %lshr to i16
+ ret i16 %trunc
+}
+
+; Negative test
+
+define i16 @lshr_16(i16 %x) {
+; CHECK-LABEL: @lshr_16(
+; CHECK-NEXT: [[ZEXT:%.*]] = zext i16 [[X:%.*]] to i32
+; CHECK-NEXT: [[LSHR:%.*]] = lshr i32 [[ZEXT]], 16
+; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[LSHR]] to i16
+; CHECK-NEXT: ret i16 [[TRUNC]]
+;
+ %zext = zext i16 %x to i32
+ %lshr = lshr i32 %zext, 16
+ %trunc = trunc i32 %lshr to i16
+ ret i16 %trunc
+}
+
+; Negative test
+
+define i16 @lshr_var_shift_amount(i8 %x, i8 %amt) {
+; CHECK-LABEL: @lshr_var_shift_amount(
+; CHECK-NEXT: [[Z:%.*]] = zext i8 [[X:%.*]] to i32
+; CHECK-NEXT: [[ZA:%.*]] = zext i8 [[AMT:%.*]] to i32
+; CHECK-NEXT: [[S:%.*]] = lshr i32 [[Z]], [[ZA]]
+; CHECK-NEXT: [[A:%.*]] = add i32 [[S]], [[Z]]
+; CHECK-NEXT: [[S2:%.*]] = lshr i32 [[A]], 2
+; CHECK-NEXT: [[T:%.*]] = trunc i32 [[S2]] to i16
+; CHECK-NEXT: ret i16 [[T]]
+;
+ %z = zext i8 %x to i32
+ %za = zext i8 %amt to i32
+ %s = lshr i32 %z, %za
+ %a = add i32 %s, %z
+ %s2 = lshr i32 %a, 2
+ %t = trunc i32 %s2 to i16
+ ret i16 %t
+}
+
+define i16 @lshr_var_bounded_shift_amount(i8 %x, i8 %amt) {
+; CHECK-LABEL: @lshr_var_bounded_shift_amount(
+; CHECK-NEXT: [[Z:%.*]] = zext i8 [[X:%.*]] to i32
+; CHECK-NEXT: [[ZA:%.*]] = zext i8 [[AMT:%.*]] to i32
+; CHECK-NEXT: [[ZA2:%.*]] = and i32 [[ZA]], 15
+; CHECK-NEXT: [[S:%.*]] = lshr i32 [[Z]], [[ZA2]]
+; CHECK-NEXT: [[A:%.*]] = add i32 [[S]], [[Z]]
+; CHECK-NEXT: [[S2:%.*]] = lshr i32 [[A]], 2
+; CHECK-NEXT: [[T:%.*]] = trunc i32 [[S2]] to i16
+; CHECK-NEXT: ret i16 [[T]]
+;
+ %z = zext i8 %x to i32
+ %za = zext i8 %amt to i32
+ %za2 = and i32 %za, 15
+ %s = lshr i32 %z, %za2
+ %a = add i32 %s, %z
+ %s2 = lshr i32 %a, 2
+ %t = trunc i32 %s2 to i16
+ ret i16 %t
+}
+
+define void @lshr_big_dag(i16* %a, i8 %b, i8 %c) {
+; CHECK-LABEL: @lshr_big_dag(
+; CHECK-NEXT: [[ZEXT1:%.*]] = zext i8 [[B:%.*]] to i32
+; CHECK-NEXT: [[ZEXT2:%.*]] = zext i8 [[C:%.*]] to i32
+; CHECK-NEXT: [[ADD1:%.*]] = add i32 [[ZEXT1]], [[ZEXT2]]
+; CHECK-NEXT: [[SFT1:%.*]] = and i32 [[ADD1]], 15
+; CHECK-NEXT: [[SHR1:%.*]] = lshr i32 [[ADD1]], [[SFT1]]
+; CHECK-NEXT: [[ADD2:%.*]] = add i32 [[ADD1]], [[SHR1]]
+; CHECK-NEXT: [[SFT2:%.*]] = and i32 [[ADD2]], 7
+; CHECK-NEXT: [[SHR2:%.*]] = lshr i32 [[ADD2]], [[SFT2]]
+; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[SHR2]] to i16
+; CHECK-NEXT: store i16 [[TRUNC]], i16* [[A:%.*]], align 2
+; CHECK-NEXT: ret void
+;
+ %zext1 = zext i8 %b to i32
+ %zext2 = zext i8 %c to i32
+ %add1 = add i32 %zext1, %zext2
+ %sft1 = and i32 %add1, 15
+ %shr1 = lshr i32 %add1, %sft1
+ %add2 = add i32 %add1, %shr1
+ %sft2 = and i32 %add2, 7
+ %shr2 = lshr i32 %add2, %sft2
+ %trunc = trunc i32 %shr2 to i16
+ store i16 %trunc, i16* %a, align 2
+ ret void
+}
+
+define <2 x i16> @lshr_vector(<2 x i8> %x) {
+; CHECK-LABEL: @lshr_vector(
+; CHECK-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i32>
+; CHECK-NEXT: [[ZA:%.*]] = and <2 x i32> [[Z]], <i32 7, i32 8>
+; CHECK-NEXT: [[S:%.*]] = lshr <2 x i32> [[Z]], [[ZA]]
+; CHECK-NEXT: [[A:%.*]] = add <2 x i32> [[S]], [[Z]]
+; CHECK-NEXT: [[S2:%.*]] = lshr <2 x i32> [[A]], <i32 4, i32 5>
+; CHECK-NEXT: [[T:%.*]] = trunc <2 x i32> [[S2]] to <2 x i16>
+; CHECK-NEXT: ret <2 x i16> [[T]]
+;
+ %z = zext <2 x i8> %x to <2 x i32>
+ %za = and <2 x i32> %z, <i32 7, i32 8>
+ %s = lshr <2 x i32> %z, %za
+ %a = add <2 x i32> %s, %z
+ %s2 = lshr <2 x i32> %a, <i32 4, i32 5>
+ %t = trunc <2 x i32> %s2 to <2 x i16>
+ ret <2 x i16> %t
+}
+
+; Negative test - can only fold to <2 x i16>, requiring new vector type
+
+define <2 x i8> @lshr_vector_no_new_vector_type(<2 x i8> %x) {
+; CHECK-LABEL: @lshr_vector_no_new_vector_type(
+; CHECK-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i32>
+; CHECK-NEXT: [[ZA:%.*]] = and <2 x i32> [[Z]], <i32 7, i32 8>
+; CHECK-NEXT: [[S:%.*]] = lshr <2 x i32> [[Z]], [[ZA]]
+; CHECK-NEXT: [[A:%.*]] = add <2 x i32> [[S]], [[Z]]
+; CHECK-NEXT: [[S2:%.*]] = lshr <2 x i32> [[A]], <i32 4, i32 5>
+; CHECK-NEXT: [[T:%.*]] = trunc <2 x i32> [[S2]] to <2 x i8>
+; CHECK-NEXT: ret <2 x i8> [[T]]
+;
+ %z = zext <2 x i8> %x to <2 x i32>
+ %za = and <2 x i32> %z, <i32 7, i32 8>
+ %s = lshr <2 x i32> %z, %za
+ %a = add <2 x i32> %s, %z
+ %s2 = lshr <2 x i32> %a, <i32 4, i32 5>
+ %t = trunc <2 x i32> %s2 to <2 x i8>
+ ret <2 x i8> %t
+}
+
+; Negative test
+
+define <2 x i16> @lshr_vector_large_shift_amount(<2 x i8> %x) {
+; CHECK-LABEL: @lshr_vector_large_shift_amount(
+; CHECK-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i32>
+; CHECK-NEXT: [[ZA:%.*]] = and <2 x i32> [[Z]], <i32 7, i32 8>
+; CHECK-NEXT: [[S:%.*]] = lshr <2 x i32> [[Z]], [[ZA]]
+; CHECK-NEXT: [[A:%.*]] = add <2 x i32> [[S]], [[Z]]
+; CHECK-NEXT: [[S2:%.*]] = lshr <2 x i32> [[A]], <i32 16, i32 5>
+; CHECK-NEXT: [[T:%.*]] = trunc <2 x i32> [[S2]] to <2 x i16>
+; CHECK-NEXT: ret <2 x i16> [[T]]
+;
+ %z = zext <2 x i8> %x to <2 x i32>
+ %za = and <2 x i32> %z, <i32 7, i32 8>
+ %s = lshr <2 x i32> %z, %za
+ %a = add <2 x i32> %s, %z
+ %s2 = lshr <2 x i32> %a, <i32 16, i32 5>
+ %t = trunc <2 x i32> %s2 to <2 x i16>
+ ret <2 x i16> %t
+}
+
+define i16 @lshr_exact(i16 %x) {
+; CHECK-LABEL: @lshr_exact(
+; CHECK-NEXT: [[ZEXT:%.*]] = zext i16 [[X:%.*]] to i32
+; CHECK-NEXT: [[LSHR:%.*]] = lshr exact i32 [[ZEXT]], 15
+; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[LSHR]] to i16
+; CHECK-NEXT: ret i16 [[TRUNC]]
+;
+ %zext = zext i16 %x to i32
+ %lshr = lshr exact i32 %zext, 15
+ %trunc = trunc i32 %lshr to i16
+ ret i16 %trunc
+}
+
+; Negative test
+
+define i16 @ashr_negative(i16 %x) {
+; CHECK-LABEL: @ashr_negative(
+; CHECK-NEXT: [[ZEXT:%.*]] = zext i16 [[X:%.*]] to i32
+; CHECK-NEXT: [[ASHR:%.*]] = ashr i32 [[ZEXT]], 15
+; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[ASHR]] to i16
+; CHECK-NEXT: ret i16 [[TRUNC]]
+;
+ %zext = zext i16 %x to i32
+ %ashr = ashr i32 %zext, 15
+ %trunc = trunc i32 %ashr to i16
+ ret i16 %trunc
+}
+
+define i16 @ashr_positive(i16 %x) {
+; CHECK-LABEL: @ashr_positive(
+; CHECK-NEXT: [[ZEXT:%.*]] = zext i16 [[X:%.*]] to i32
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[ZEXT]], 32767
+; CHECK-NEXT: [[ASHR:%.*]] = ashr i32 [[AND]], 15
+; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[ASHR]] to i16
+; CHECK-NEXT: ret i16 [[TRUNC]]
+;
+ %zext = zext i16 %x to i32
+ %and = and i32 %zext, 32767
+ %ashr = ashr i32 %and, 15
+ %trunc = trunc i32 %ashr to i16
+ ret i16 %trunc
+}
+
+define i16 @ashr_exact(i16 %x) {
+; CHECK-LABEL: @ashr_exact(
+; CHECK-NEXT: [[ZEXT:%.*]] = zext i16 [[X:%.*]] to i32
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[ZEXT]], 32767
+; CHECK-NEXT: [[ASHR:%.*]] = ashr exact i32 [[AND]], 15
+; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[ASHR]] to i16
+; CHECK-NEXT: ret i16 [[TRUNC]]
+;
+ %zext = zext i16 %x to i32
+ %and = and i32 %zext, 32767
+ %ashr = ashr exact i32 %and, 15
+ %trunc = trunc i32 %ashr to i16
+ ret i16 %trunc
+}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/pr50555.ll b/llvm/test/Transforms/PhaseOrdering/X86/pr50555.ll
similarity index 98%
rename from llvm/test/Transforms/SLPVectorizer/X86/pr50555.ll
rename to llvm/test/Transforms/PhaseOrdering/X86/pr50555.ll
index 818ba6450fcb6..da457578a79c1 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/pr50555.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/pr50555.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -mtriple=x86_64-- -aggressive-instcombine -slp-vectorizer -dce -S | FileCheck %s --check-prefixes=SSE
-; RUN: opt < %s -mtriple=x86_64-- -mcpu=corei7-avx -aggressive-instcombine -slp-vectorizer -dce -S | FileCheck %s --check-prefixes=AVX
+; RUN: opt < %s -O3 -S -mtriple=x86_64-- | FileCheck %s --check-prefixes=SSE
+; RUN: opt < %s -O3 -S -mtriple=x86_64-- -mattr=avx | FileCheck %s --check-prefixes=AVX
define void @trunc_through_one_add(i16* noalias %0, i8* noalias readonly %1) {
; SSE-LABEL: @trunc_through_one_add(
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