[PATCH] D108091: [AggressiveInstCombine] Add shift left instruction to `TruncInstCombine` DAG

[Anton Afanasyev via Phabricator via llvm-commits]

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Add `shl` instruction to the DAG post-dominated by `trunc`, allowing
TruncInstCombine to reduce bitwidth of expressions containing left shifts.

Part of https://reviews.llvm.org/D107766


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D108091

Files:
  llvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp
  llvm/test/Transforms/AggressiveInstCombine/trunc_shifts.ll

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