[PATCH] D107880: [AArch64][SVE] Remove assertion/range check for i16 values during immediate selection

[Usman Nadeem via Phabricator via llvm-commits]

mnadeem added inline comments.


================
Comment at: llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll:806
+;
+define <vscale x 8 x i16> @uqsub(<vscale x 8 x i16> %a) {
+; CHECK-LABEL: uqsub:
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efriedma wrote:
> Please stick this next to the other tests in llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-imm.ll .
Looks like tests in that file explicitly call the sve intrinsics while this test does not.
There are similar min/max tests above so I think it will be okay here, or should I move it?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107880/new/

https://reviews.llvm.org/D107880